/*******************************************************************************
 *
 * $Id: $
 * Copyright: (c) 2018 Broadcom. All Rights Reserved. "Broadcom" refers to 
 * Broadcom Limited and/or its subsidiaries.
 * 
 * Broadcom Switch Software License
 * 
 * This license governs the use of the accompanying Broadcom software. Your 
 * use of the software indicates your acceptance of the terms and conditions 
 * of this license. If you do not agree to the terms and conditions of this 
 * license, do not use the software.
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 *    grants to you a perpetual, worldwide, non-exclusive, and royalty-free 
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 *    intended for use, with a Broadcom switch integrated circuit.
 *    No Reverse Engineering. You will not use the Work to disassemble, 
 *    reverse engineer, decompile, or attempt to ascertain the underlying 
 *    technology of a Broadcom switch integrated circuit.
 * 8. Termination
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 *    license (including the license grants of Sections 2 and 3) will 
 *    terminate immediately.
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 * 10. Limitation of Liability
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 * 
 *
 * DO NOT EDIT THIS FILE!
 * This file is auto-generated from the registers file.
 * Edits to this file will be lost when it is regenerated.
 *
 * Symbol table file for the BCMI_FALCON_XGXS.
 * This symbol table is used by the Broadcom debug shell.
 */


#include <phymod/chip/bcmi_falcon_xgxs_defs.h>
#include <phymod/phymod_symbols.h>

/* No symbols will be compiled unless this is defined. */
#if PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS == 1
/*******************************************************************************
 *
 * If PHYMOD_CONFIG_INCLUDE_FIELD_INFO is 1, then symbol information
 * necessary to encode and decode the individual fields of a register or memory
 * will be available.
 *
 * Without it, only the register and memory names will be symbolically available
 * and their values will be displayed as raw data only. 
 *
 * Field information can be compiled out in the interest of saving code space.
 */
#if PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS

static uint32_t BCMI_FALCON_XGXS_ACC_ADDR_DATAr_fields[] =
{
    /* MDIO_ADDR_DATA:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(361, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_ACC_CTLr_fields[] =
{
    /* MDIO_DEVAD:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(365, 4, 0),
    /* MDIO_FUNCTION:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(372, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL0r_fields[] =
{
    /* AMS_PLL_SET_CLK4TSC:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(75, 1, 0),
    /* AMS_PLL_IMIN_ICLKINT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(44, 2, 2),
    /* AMS_PLL_IMAX_ICLKINT:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(33, 3, 3),
    /* AMS_PLL_IMODE_ICLKINT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(55, 4, 4),
    /* AMS_PLL_IMIN_ICLKODRV1:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(45, 5, 5),
    /* AMS_PLL_IMAX_ICLKODRV1:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(34, 6, 6),
    /* AMS_PLL_IMODE_ICLKODRV1:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(56, 7, 7),
    /* AMS_PLL_IMIN_ICLKIDRV1:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(43, 8, 8),
    /* AMS_PLL_IMAX_ICLKIDRV1:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(32, 9, 9),
    /* AMS_PLL_IMODE_ICLKIDRV1:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(54, 10, 10),
    /* AMS_PLL_CAL_OFF:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(22, 11, 11),
    /* AMS_PLL_CAL_AUX:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(21, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL1r_fields[] =
{
    /* AMS_PLL_IMIN_ICKGEN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(42, 0, 0),
    /* AMS_PLL_IMAX_ICKGEN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(31, 1, 1),
    /* AMS_PLL_IMODE_ICKGEN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(53, 2, 2),
    /* AMS_PLL_DRV_HV_DISABLE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(24, 3, 3),
    /* AMS_PLL_TEST_BG_OPAMP_BIAS:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(80, 5, 4),
    /* AMS_PLL_SPARE_23_22:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(78, 7, 6),
    /* AMS_PLL_VCOICTRL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(88, 9, 8),
    /* AMS_PLL_VCO_INDICATOR:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(89, 10, 10),
    /* AMS_PLL_IVCO:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(63, 13, 11),
    /* AMS_PLL_RESET:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(74, 14, 14),
    /* AMS_PLL_ENABLE_FTUNE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(25, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL2r_fields[] =
{
    /* AMS_PLL_EN_HRZ:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(26, 0, 0),
    /* AMS_PLL_IQP:1:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(62, 4, 1),
    /* AMS_PLL_REFL_PLL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(73, 5, 5),
    /* AMS_PLL_REFH_PLL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(72, 6, 6),
    /* AMS_PLL_IMIN_IBIAS:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(40, 7, 7),
    /* AMS_PLL_IMODE_IBIAS:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(51, 8, 8),
    /* AMS_PLL_IMAX_IBIAS:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(29, 9, 9),
    /* AMS_PLL_IMIN_ICP:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(48, 10, 10),
    /* AMS_PLL_IMODE_ICP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(59, 11, 11),
    /* AMS_PLL_IMAX_ICP:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(37, 12, 12),
    /* AMS_PLL_IMIN_ICK:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(41, 13, 13),
    /* AMS_PLL_IMODE_ICK:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(52, 14, 14),
    /* AMS_PLL_IMAX_ICK:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(30, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL3r_fields[] =
{
    /* AMS_PLL_IMIN_IRXCLKBUF:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(50, 0, 0),
    /* AMS_PLL_IMODE_IRXCLKBUF:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(61, 1, 1),
    /* AMS_PLL_IMAX_IRXCLKBUF:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(39, 2, 2),
    /* AMS_PLL_IMIN_ICMLDIV:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(46, 3, 3),
    /* AMS_PLL_IMODE_ICMLDIV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(57, 4, 4),
    /* AMS_PLL_IMAX_ICMLDIV:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(35, 5, 5),
    /* AMS_PLL_IMIN_ICOMP:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(47, 6, 6),
    /* AMS_PLL_IMODE_ICOMP:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(58, 7, 7),
    /* AMS_PLL_IMAX_ICOMP:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(36, 8, 8),
    /* AMS_PLL_IMIN_IOP:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(49, 9, 9),
    /* AMS_PLL_IMODE_IOP:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(60, 10, 10),
    /* AMS_PLL_IMAX_IOP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(38, 11, 11),
    /* AMS_PLL_TEST_VREF:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(86, 12, 12),
    /* AMS_PLL_TEST_VC:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(85, 13, 13),
    /* AMS_PLL_TEST_PLL:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(81, 14, 14),
    /* AMS_PLL_TEST_RX:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(84, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL4r_fields[] =
{
    /* AMS_PLL_BGR_PTATADJ:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(20, 3, 0),
    /* AMS_PLL_BGR_CTATADJ:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(19, 7, 4),
    /* AMS_PLL_PLL2RX_CLKBW:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(71, 9, 8),
    /* AMS_PLL_COMP_VTH:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(23, 10, 10),
    /* AMS_PLL_VDDR_BGB:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(90, 11, 11),
    /* AMS_PLL_KVH_FORCE:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(64, 13, 12),
    /* AMS_PLL_FORCE_KVH_BW:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(27, 14, 14),
    /* AMS_PLL_FORCE_RESCAL:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(28, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL5r_fields[] =
{
    /* AMS_PLL_TEST_PORT_MAX_AMPLITUDE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(83, 0, 0),
    /* AMS_PLL_BGIP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(18, 1, 1),
    /* AMS_PLL_BGINT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(17, 2, 2),
    /* AMS_PLL_VBYPASS:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(87, 3, 3),
    /* AMS_PLL_TEST_PNP:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(82, 5, 4),
    /* AMS_PLL_MIX3P1C_CALR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(69, 10, 6),
    /* AMS_PLL_MIX3P1C_CALR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(70, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL6r_fields[] =
{
    /* AMS_PLL_SPARE_101_96:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(76, 5, 0),
    /* AMS_PLL_MIX1P2CR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(65, 10, 6),
    /* AMS_PLL_MIX1P2CR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(66, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_CTL7r_fields[] =
{
    /* AMS_PLL_SPARE_117_112:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(77, 5, 0),
    /* AMS_PLL_MIX3P1CR_CTATADJ:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(67, 10, 6),
    /* AMS_PLL_MIX3P1CR_PTATADJ:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(68, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_AMS_PLL_STSr_fields[] =
{
    /* AMS_PLL_STS:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(79, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL0r_fields[] =
{
    /* AMS_RX_MASTER_DIODES_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(109, 2, 0),
    /* AMS_RX_SIGDET_THRESHOLD:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(127, 5, 3),
    /* AMS_RX_SIGDET_PWRDN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(126, 6, 6),
    /* AMS_RX_SIGDET_BYPASS:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(123, 7, 7),
    /* AMS_RX_TPORT_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(140, 8, 8),
    /* AMS_RX_VGA_10G_BW:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(149, 9, 9),
    /* AMS_RX_EQ_LZ_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(107, 10, 10),
    /* AMS_RX_DFE_HGAIN_EN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(100, 11, 11),
    /* AMS_RX_DC_COUPLE:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(97, 12, 12),
    /* AMS_RX_PEAKING_FILTER_IBIAS:13:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(114, 15, 13)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL1r_fields[] =
{
    /* AMS_RX_SPARE_16:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(134, 0, 0),
    /* AMS_RX_VGA0_IBIAS:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(141, 3, 1),
    /* AMS_RX_VGA1_IBIAS:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(143, 6, 4),
    /* AMS_RX_VGA2_IBIAS:7:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(145, 9, 7),
    /* AMS_RX_VGA3_IBIAS:10:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(147, 12, 10),
    /* AMS_RX_CM_VOLTAGE_IBIAS:13:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(92, 15, 13)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL2r_fields[] =
{
    /* AMS_RX_SIGDET_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(124, 2, 0),
    /* AMS_RX_PHASE_INTERPOLATORS_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(116, 5, 3),
    /* AMS_RX_DFE_TAP_WEIGHT_IBIAS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(104, 8, 6),
    /* AMS_RX_SEL_UGBW:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(121, 10, 9),
    /* AMS_RX_SEL_TH4DFE:11:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(120, 12, 11),
    /* AMS_RX_PD_CH_P1:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(113, 13, 13),
    /* AMS_RX_SIGDET_POWER_SAVE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(125, 14, 14),
    /* AMS_RX_PWRDN_FTAP:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(117, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL3r_fields[] =
{
    /* AMS_RX_MET_R_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(110, 2, 0),
    /* AMS_RX_DLL_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(105, 5, 3),
    /* AMS_RX_OFFSET_CORRECTION_IBIAS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(111, 8, 6),
    /* AMS_RX_DFE_SUM_BUF_IBIAS:9:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(103, 11, 9),
    /* AMS_RX_DFE_SLICER_IBIAS:12:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(102, 14, 12),
    /* AMS_RX_SPARE_63:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(135, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL4r_fields[] =
{
    /* AMS_RX_DFE_SLICER_CAL_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(101, 2, 0),
    /* AMS_RX_TBD_IBIAS:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(138, 5, 3),
    /* AMS_RX_VGA0_RESCAL_MUX:6:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(142, 10, 6),
    /* AMS_RX_VGA1_RESCAL_MUX:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(144, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL5r_fields[] =
{
    /* AMS_RX_VGA2_RESCAL_MUX:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(146, 4, 0),
    /* AMS_RX_VGA3_RESCAL_MUX:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(148, 9, 5),
    /* AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX:10:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(139, 14, 10),
    /* AMS_RX_SPARE_95:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(136, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL6r_fields[] =
{
    /* AMS_RX_PEAKING_FILTER_RESCAL_MUX:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(115, 3, 0),
    /* AMS_RX_OFFSET_CORRECTION_RESCAL_MUX:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(112, 7, 4),
    /* AMS_RX_SPARE_111_104:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(128, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL7r_fields[] =
{
    /* AMS_RX_DC_OFFSET:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(98, 6, 0),
    /* AMS_RX_FORCE_DC_OFFSET:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(108, 7, 7),
    /* AMS_RX_DC_OFFSET_RANGE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(99, 8, 8),
    /* AMS_RX_RX_OFFSET_PD:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(118, 9, 9),
    /* AMS_RX_SHORT_VGA_OUTPUT:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(122, 10, 10),
    /* AMS_RX_SPARE_123:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(129, 11, 11),
    /* AMS_RX_VGA_LOW_GAIN:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(150, 13, 12),
    /* AMS_RX_VGA_STEP_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(151, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL8r_fields[] =
{
    /* AMS_RX_DAC4CK_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(95, 5, 0),
    /* AMS_RX_SPARE_135_134:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(130, 7, 6),
    /* AMS_RX_DAC4CK_PHS:8:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(96, 13, 8),
    /* AMS_RX_SPARE_143_142:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(131, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_CTL9r_fields[] =
{
    /* AMS_RX_DAC4CK_DAT:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(94, 5, 0),
    /* AMS_RX_SPARE_151_150:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(132, 7, 6),
    /* AMS_RX_CLK_BW_CTRL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(91, 9, 8),
    /* AMS_RX_EN_TAP9DELAY:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(106, 10, 10),
    /* AMS_RX_SEL_D2CLP:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(119, 11, 11),
    /* AMS_RX_D2C_CLKBUF_IBIAS:12:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(93, 14, 12),
    /* AMS_RX_SPARE_159:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(133, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_RX_STSr_fields[] =
{
    /* AMS_RX_STS:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(137, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL0r_fields[] =
{
    /* AMS_TX_SPARE_0:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(168, 0, 0),
    /* AMS_TX_SPARE_3_1:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(171, 3, 1),
    /* AMS_TX_TEST_DATA:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(174, 5, 4),
    /* AMS_TX_TICKSEL:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(175, 7, 6),
    /* AMS_TX_VDDR_BGB:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(176, 8, 8),
    /* AMS_TX_DCC_SEL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(156, 9, 9),
    /* AMS_TX_DCC_DIS:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(155, 10, 10),
    /* AMS_TX_CAL_OFF:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(154, 11, 11),
    /* AMS_TX_CAL_AUX:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(153, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL1r_fields[] =
{
    /* AMS_TX_IBIAS:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(159, 2, 0),
    /* AMS_TX_SPARE_21_19:3:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(169, 5, 3),
    /* AMS_TX_ICML:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(160, 8, 6),
    /* AMS_TX_ILDO:9:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(161, 11, 9),
    /* AMS_TX_LDO_VREF:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(162, 13, 12),
    /* AMS_TX_SEL_EMPH_MODE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(165, 14, 14),
    /* AMS_TX_SPARE_31:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(170, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL2r_fields[] =
{
    /* AMS_TX_AMP_CTL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(152, 3, 0),
    /* AMS_TX_POST3_COEF:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(164, 6, 4),
    /* AMS_TX_SIGN_POST3:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(167, 7, 7),
    /* AMS_TX_POST2_COEF:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(163, 11, 8),
    /* AMS_TX_SIGN_POST2:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(166, 12, 12),
    /* AMS_TX_DRIVERMODE:13:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(157, 14, 13),
    /* AMS_TX_ELEC_IDLE_AUX:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(158, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_AMS_TX_CTL3r_fields[] =
{
    /* AMS_TX_SPARE_63_48:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(172, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_AMS_TX_STSr_fields[] =
{
    /* AMS_TX_STS:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(173, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields[] =
{
    /* LN_RX_S_CLKGATE_FRC_ON:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(348, 0, 0),
    /* LN_RX_S_COMCLK_SEL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(350, 1, 1),
    /* LN_RX_S_COMCLK_FRC_ON:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(349, 2, 2),
    /* PMD_RX_CLK_VLD_FRC:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(494, 3, 3),
    /* PMD_RX_CLK_VLD_FRC_VAL:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(495, 4, 4)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields[] =
{
    /* AFE_RX_PWRDN_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(1, 0, 0),
    /* AFE_RX_PWRDN_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(2, 1, 1),
    /* AFE_RX_RESET_FRC:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(5, 2, 2),
    /* AFE_RX_RESET_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(6, 3, 3),
    /* AFE_TX_PWRDN_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(13, 4, 4),
    /* AFE_TX_PWRDN_FRC_VAL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(14, 5, 5),
    /* AFE_TX_RESET_FRC:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(15, 6, 6),
    /* AFE_TX_RESET_FRC_VAL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(16, 7, 7),
    /* AFE_RX_RCLK20_PWRDN_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(3, 8, 8),
    /* AFE_RX_RCLK20_PWRDN_FRC_VAL:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(4, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields[] =
{
    /* LN_DP_S_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(346, 1, 1),
    /* LN_RX_S_PWRDN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(351, 2, 2),
    /* LN_TX_S_PWRDN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(355, 3, 3),
    /* AFE_SIGDET_PWRDN:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(7, 4, 4)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr_fields[] =
{
    /* LN_RX_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(352, 0, 0),
    /* LN_RX_DP_S_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(347, 1, 1),
    /* SIGDET_DP_RSTB_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(694, 2, 2),
    /* LN_TX_S_RSTB:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(356, 8, 8),
    /* LN_TX_DP_S_RSTB:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(354, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr_fields[] =
{
    /* LANE_DP_RESET_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(341, 2, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_MASKr_fields[] =
{
    /* LANE_MULTICAST_MASK_CONTROL:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(342, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields[] =
{
    /* PMD_LN_H_RSTB_PKILL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(490, 0, 0),
    /* PMD_LN_DP_H_RSTB_PKILL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(489, 1, 1),
    /* PMD_LN_RX_H_PWRDN_PKILL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(491, 2, 2),
    /* PMD_LN_TX_H_PWRDN_PKILL:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(492, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr_fields[] =
{
    /* LANE_REG_RESET_OCCURRED:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(343, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr_fields[] =
{
    /* LN_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(353, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr_fields[] =
{
    /* OSR_MODE_FRC_VAL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(444, 3, 0),
    /* OSR_MODE_FRC:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(443, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr_fields[] =
{
    /* OSR_MODE_PIN:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(445, 3, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr_fields[] =
{
    /* OSR_MODE:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(442, 3, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr_fields[] =
{
    /* PMD_LANE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(488, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr_fields[] =
{
    /* UC_ACK_LANE_CFG_DONE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(818, 0, 0),
    /* UC_ACK_LANE_DP_RESET:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(819, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields[] =
{
    /* CL93N72_IEEE_LP_COEFF_UPDATE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(232, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields[] =
{
    /* CL93N72_IEEE_LP_STATUS_REPORT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(233, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields[] =
{
    /* CL93N72_IEEE_LD_COEFF_UPDATE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(230, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields[] =
{
    /* CL93N72_IEEE_LD_STATUS_REPORT:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(231, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields[] =
{
    /* CL93N72_IEEE_RESTART_TRAINING:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(235, 0, 0),
    /* CL93N72_IEEE_TRAINING_ENABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(236, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields[] =
{
    /* CL93N72_IEEE_RECEIVER_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(234, 0, 0),
    /* CL93N72_IEEE_FRAME_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(229, 1, 1),
    /* CL93N72_IEEE_TRAINING_STATUS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(238, 2, 2),
    /* CL93N72_IEEE_TRAINING_FAILURE:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(237, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL0r_fields[] =
{
    /* CL93N72_RX_TRAINING_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(251, 0, 0),
    /* CL93N72_TR_COARSE_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(258, 1, 1),
    /* CL93N72_RX_SIGNAL_OK:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(250, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL1r_fields[] =
{
    /* CL93N72_GOOD_MARKER_CNT:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(228, 1, 0),
    /* CL93N72_BAD_MARKER_CNT:4:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(219, 6, 4)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_CTL2r_fields[] =
{
    /* CL93N72_CTRL_FRAME_DLY:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(223, 3, 0),
    /* CL93N72_DME_CELL_BOUNDARY_CHK:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(225, 4, 4),
    /* CL93N72_STRICT_DME_CHK:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(252, 5, 5),
    /* CL93N72_STRICT_MARKER_CHK:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(253, 6, 6),
    /* CL93N72_PPM_OFFSET_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(247, 7, 7),
    /* CL93N72_RX_DP_LN_CLK_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(249, 8, 8),
    /* CL93N72_FRAME_CONSISTENCY_CHK_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(226, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_STS0r_fields[] =
{
    /* CL93N72_FRAME_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(227, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields[] =
{
    /* CL93N72_MICRO_UPDATE_CHG_INT_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(245, 0, 0),
    /* CL93N72_MICRO_STATUS_CHG_INT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(243, 1, 1),
    /* CL93N72_MICRO_FRAME_LOCK_INT_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(241, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r_fields[] =
{
    /* CL93N72_MICRO_UPDATE_CHG_LSTATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(246, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r_fields[] =
{
    /* CL93N72_MICRO_STATUS_CHG_LSTATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(244, 0, 0),
    /* CL93N72_MICRO_FRAME_LOCK_LSTATUS:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(242, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL0r_fields[] =
{
    /* CL93N72_SW_RX_TRAINED:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(256, 0, 0),
    /* CL93N72_SW_FRAME_LOCK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(254, 1, 1),
    /* CL93N72_SW_REMOTE_RX_READY:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(255, 2, 2),
    /* CL93N72_PRBS_SEL:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(248, 6, 4),
    /* CL93N72_CL93PRBSSEED_ORDER:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(221, 7, 7),
    /* CL93N72_CL93PRBSSEED_RANDOM:8:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(222, 8, 8)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL1r_fields[] =
{
    /* CL93N72_BRK_RING_OSC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(220, 0, 0),
    /* CL93N72_DIS_MAX_WAIT_TIMER:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(224, 1, 1),
    /* CL93N72_TX_DP_LN_CLK_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(262, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL2r_fields[] =
{
    /* CL93N72_TXFIR_PRE:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(261, 4, 0),
    /* CL93N72_TXFIR_POST:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(260, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_CTL3r_fields[] =
{
    /* CL93N72_TXFIR_MAIN:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(259, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields[] =
{
    /* CL93N72_LD_XMT_STATUS_PAGE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(239, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_STS0r_fields[] =
{
    /* CL93N72_LOCAL_RX_READY:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(240, 0, 0),
    /* CL93N72_TRAINING_FSM_SIGNAL_DETECT:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(257, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields[] =
{
    /* CL93N72_XMT_UPDATE_PAGE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(263, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr_fields[] =
{
    /* CORE_DP_RESET_STATE:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(264, 2, 0),
    /* LANE_RESET_RELEASED_INDEX:8:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(345, 12, 8),
    /* LANE_RESET_RELEASED:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(344, 14, 14)
};
static uint32_t BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr_fields[] =
{
    /* CORE_REG_RESET_OCCURRED:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(267, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r_fields[] =
{
    /* LANE_ADDR_2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(339, 4, 0),
    /* LANE_ADDR_3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(340, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_DIG_LN_MASKr_fields[] =
{
    /* CORE_MULTICAST_MASK_CONTROL:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(266, 3, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr_fields[] =
{
    /* PMD_CORE_MODE:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(487, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_REVID0r_fields[] =
{
    /* REVID_MODEL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(545, 5, 0),
    /* REVID_PROCESS:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(548, 8, 6),
    /* REVID_BONDING:9:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(539, 10, 9),
    /* REVID_REV_NUMBER:11:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(550, 13, 11),
    /* REVID_REV_LETTER:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(549, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DIG_REVID1r_fields[] =
{
    /* REVID_EEE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(541, 0, 0),
    /* REVID_LLP:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(542, 1, 1),
    /* REVID_PIR:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(547, 2, 2),
    /* REVID_CL72:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(540, 3, 3),
    /* REVID_MICRO:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(544, 4, 4),
    /* REVID_MDIO:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(543, 5, 5),
    /* REVID_MULTIPLICITY:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(546, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DIG_REVID2r_fields[] =
{
    /* REVID2:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(538, 3, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr_fields[] =
{
    /* PMD_CORE_DP_H_RSTB_PKILL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(486, 1, 1),
    /* SUP_RST_SEQ_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(706, 3, 3),
    /* SUP_RST_SEQ_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(705, 4, 4),
    /* PMD_MDIO_TRANS_PKILL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(493, 5, 5),
    /* PMD_TX_CLK_VLD_FRC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(498, 7, 7),
    /* PMD_TX_CLK_VLD_FRC_VAL:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(499, 8, 8),
    /* TX_S_COMCLK_SEL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(812, 9, 9),
    /* TX_S_COMCLK_FRC_ON:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(811, 10, 10),
    /* TX_S_CLKGATE_FRC_ON:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(810, 11, 11),
    /* AFE_S_PLL_RESET_FRC_VAL:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(12, 12, 12),
    /* AFE_S_PLL_RESET_FRC:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(11, 13, 13),
    /* TX_PI_LOOP_FILTER_STABLE:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(794, 14, 14)
};
static uint32_t BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr_fields[] =
{
    /* CORE_S_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(268, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr_fields[] =
{
    /* RST_SEQ_TIMER:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(557, 2, 0),
    /* PWRDN_SEQ_TIMER:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(527, 10, 8),
    /* RST_SEQ_DIS_FLT_MODE:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(556, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r_fields[] =
{
    /* HEARTBEAT_COUNT_1US:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(330, 9, 0),
    /* CORE_DP_S_RSTB:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(265, 13, 13),
    /* AFE_S_PLL_PWRDN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(10, 14, 14),
    /* UC_ACTIVE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(820, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r_fields[] =
{
    /* TX_LANE_MAP_0:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(773, 4, 0),
    /* TX_LANE_MAP_1:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(774, 9, 5),
    /* TX_LANE_MAP_2:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(775, 14, 10)
};
static uint32_t BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields[] =
{
    /* TX_LANE_MAP_3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(776, 4, 0),
    /* LANE_ADDR_0:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(337, 9, 5),
    /* LANE_ADDR_1:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(338, 14, 10)
};
static uint32_t BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr_fields[] =
{
    /* UC_ACK_CORE_CFG_DONE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(813, 0, 0),
    /* UC_ACK_CORE_DP_RESET:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(814, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_1G_STSr_fields[] =
{
    /* CDR_1G_PHASE_POINTER:0:7 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(194, 7, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL0r_fields[] =
{
    /* OS_ALL_EDGES:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(446, 0, 0),
    /* BR_PD_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(177, 1, 1),
    /* OS_PATTERN_ENHANCED:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(447, 2, 2),
    /* CDR_FREQ_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(203, 3, 3),
    /* CDR_INTEG_REG_CLR:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(209, 5, 5),
    /* CDR_PHASE_ERR_FRZ:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(214, 6, 6),
    /* CDR_INTEG_SAT_SEL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(210, 7, 7),
    /* CDR_FREQ_OVERRIDE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(204, 8, 8),
    /* CDR_ZERO_POLARITY:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(217, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL1r_fields[] =
{
    /* CDR_FREQ_OVERRIDE_VAL:5:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(205, 15, 5)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_CTL2r_fields[] =
{
    /* CDR_LM_THR_SEL:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(212, 3, 0),
    /* CDR_1G_SWAP_PZ:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(195, 4, 4),
    /* CDR_1G_FORCE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(191, 5, 5),
    /* TX_PI_LOOP_TIMING_SRC_SEL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(795, 6, 6),
    /* PHS_SUM_IGNORE_DSC_LOCK:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(468, 7, 7),
    /* CDR_1G_MANUAL_MODE:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(192, 8, 8),
    /* CDR_1G_MANUAL_STROBE:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(193, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr_fields[] =
{
    /* CDR_INTEG_REG:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(208, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr_fields[] =
{
    /* CDR_LM_OUTOFLOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(211, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr_fields[] =
{
    /* CDR_PHASE_ERROR:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(213, 5, 0),
    /* CDR_VCO_REG:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(216, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr_fields[] =
{
    /* THRESH_TIMER_T1:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(714, 1, 0),
    /* THRESH_STEP_SIZE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(713, 5, 4),
    /* DATA_THRESH_SEL_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(269, 14, 8),
    /* DATA_THRESH_WRITE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(270, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr_fields[] =
{
    /* DC_OFFS_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(279, 0, 0),
    /* DC_OFFS_HYS_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(282, 2, 2),
    /* DC_OFFS_HYS_MAG:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(283, 3, 3),
    /* DC_OFFS_GRADIENT_INVERT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(281, 4, 4),
    /* DC_OFFS_GAIN:5:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(280, 6, 5),
    /* DC_OFFS_ACC_CLR:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(278, 7, 7),
    /* DC_OFFS_WRITE_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(286, 14, 8),
    /* DC_OFFS_WRITE_FRC_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(285, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr_fields[] =
{
    /* DC_OFFSET_BIN:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(277, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr_fields[] =
{
    /* PRESET_DSC_AFE_BANK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(522, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_PRESETr_fields[] =
{
    /* PRESET_DSC_C_BANK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(524, 0, 0),
    /* PRESET_DSC_D_BANK:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(525, 1, 1),
    /* PRESET_DSC_A_BANK:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(523, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(607, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_LMS:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(581, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields[] =
{
    /* RXA_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(580, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(579, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields[] =
{
    /* RXA_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(583, 5, 0),
    /* RXA_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(582, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(606, 5, 0),
    /* RXB_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(605, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields[] =
{
    /* RXB_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(609, 5, 0),
    /* RXB_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(608, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_LMS:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(659, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_LMS:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(633, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields[] =
{
    /* RXC_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(632, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(631, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields[] =
{
    /* RXC_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(635, 5, 0),
    /* RXC_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(634, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_DP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(658, 5, 0),
    /* RXD_SLICER_OFFSET_ADJ_DN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(657, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields[] =
{
    /* RXD_SLICER_OFFSET_ADJ_ZP:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(661, 5, 0),
    /* RXD_SLICER_OFFSET_ADJ_ZN:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(660, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r_fields[] =
{
    /* RX_DATA_15_TO_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(662, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r_fields[] =
{
    /* RX_DATA_35_TO_20:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(663, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields[] =
{
    /* RXD_DFE_TAP10:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(636, 3, 0),
    /* RXC_DFE_TAP10:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(610, 7, 4),
    /* RXB_DFE_TAP10:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(584, 11, 8),
    /* RXA_DFE_TAP10:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(558, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields[] =
{
    /* RXD_DFE_TAP12_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(641, 1, 0),
    /* RXD_DFE_TAP11_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(639, 3, 2),
    /* RXC_DFE_TAP12_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(615, 5, 4),
    /* RXC_DFE_TAP11_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(613, 7, 6),
    /* RXB_DFE_TAP12_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(589, 9, 8),
    /* RXB_DFE_TAP11_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(587, 11, 10),
    /* RXA_DFE_TAP12_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(563, 13, 12),
    /* RXA_DFE_TAP11_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(561, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields[] =
{
    /* RXD_DFE_TAP11:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(638, 3, 0),
    /* RXC_DFE_TAP11:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(612, 7, 4),
    /* RXB_DFE_TAP11:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(586, 11, 8),
    /* RXA_DFE_TAP11:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(560, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields[] =
{
    /* RXD_DFE_TAP12:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(640, 3, 0),
    /* RXC_DFE_TAP12:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(614, 7, 4),
    /* RXB_DFE_TAP12:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(588, 11, 8),
    /* RXA_DFE_TAP12:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(562, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields[] =
{
    /* RXD_DFE_TAP14_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(645, 1, 0),
    /* RXD_DFE_TAP13_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(643, 3, 2),
    /* RXC_DFE_TAP14_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(619, 5, 4),
    /* RXC_DFE_TAP13_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(617, 7, 6),
    /* RXB_DFE_TAP14_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(593, 9, 8),
    /* RXB_DFE_TAP13_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(591, 11, 10),
    /* RXA_DFE_TAP14_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(567, 13, 12),
    /* RXA_DFE_TAP13_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(565, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields[] =
{
    /* RXD_DFE_TAP13:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(642, 3, 0),
    /* RXC_DFE_TAP13:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(616, 7, 4),
    /* RXB_DFE_TAP13:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(590, 11, 8),
    /* RXA_DFE_TAP13:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(564, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields[] =
{
    /* RXD_DFE_TAP14:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(644, 3, 0),
    /* RXC_DFE_TAP14:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(618, 7, 4),
    /* RXB_DFE_TAP14:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(592, 11, 8),
    /* RXA_DFE_TAP14:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(566, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr_fields[] =
{
    /* RXB_DFE_TAP2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(594, 4, 0),
    /* RXA_DFE_TAP2:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(568, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr_fields[] =
{
    /* RXD_DFE_TAP2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(646, 4, 0),
    /* RXC_DFE_TAP2:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(620, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr_fields[] =
{
    /* RXB_DFE_TAP3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(595, 4, 0),
    /* RXA_DFE_TAP3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(569, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr_fields[] =
{
    /* RXD_DFE_TAP3:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(647, 4, 0),
    /* RXC_DFE_TAP3:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(621, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields[] =
{
    /* RXD_DFE_TAP4:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(648, 3, 0),
    /* RXC_DFE_TAP4:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(622, 7, 4),
    /* RXB_DFE_TAP4:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(596, 11, 8),
    /* RXA_DFE_TAP4:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(570, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields[] =
{
    /* RXD_DFE_TAP5:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(649, 3, 0),
    /* RXC_DFE_TAP5:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(623, 7, 4),
    /* RXB_DFE_TAP5:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(597, 11, 8),
    /* RXA_DFE_TAP5:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(571, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields[] =
{
    /* RXD_DFE_TAP6:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(650, 3, 0),
    /* RXC_DFE_TAP6:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(624, 7, 4),
    /* RXB_DFE_TAP6:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(598, 11, 8),
    /* RXA_DFE_TAP6:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(572, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields[] =
{
    /* RXD_DFE_TAP8_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(654, 1, 0),
    /* RXD_DFE_TAP7_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(652, 3, 2),
    /* RXC_DFE_TAP8_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(628, 5, 4),
    /* RXC_DFE_TAP7_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(626, 7, 6),
    /* RXB_DFE_TAP8_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(602, 9, 8),
    /* RXB_DFE_TAP7_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(600, 11, 10),
    /* RXA_DFE_TAP8_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(576, 13, 12),
    /* RXA_DFE_TAP7_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(574, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields[] =
{
    /* RXD_DFE_TAP7:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(651, 3, 0),
    /* RXC_DFE_TAP7:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(625, 7, 4),
    /* RXB_DFE_TAP7:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(599, 11, 8),
    /* RXA_DFE_TAP7:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(573, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields[] =
{
    /* RXD_DFE_TAP8:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(653, 3, 0),
    /* RXC_DFE_TAP8:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(627, 7, 4),
    /* RXB_DFE_TAP8:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(601, 11, 8),
    /* RXA_DFE_TAP8:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(575, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields[] =
{
    /* RXD_DFE_TAP10_MUX:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(637, 1, 0),
    /* RXD_DFE_TAP9_MUX:2:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(656, 3, 2),
    /* RXC_DFE_TAP10_MUX:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(611, 5, 4),
    /* RXC_DFE_TAP9_MUX:6:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(630, 7, 6),
    /* RXB_DFE_TAP10_MUX:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(585, 9, 8),
    /* RXB_DFE_TAP9_MUX:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(604, 11, 10),
    /* RXA_DFE_TAP10_MUX:12:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(559, 13, 12),
    /* RXA_DFE_TAP9_MUX:14:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(578, 15, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields[] =
{
    /* RXD_DFE_TAP9:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(655, 3, 0),
    /* RXC_DFE_TAP9:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(629, 7, 4),
    /* RXB_DFE_TAP9:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(603, 11, 8),
    /* RXA_DFE_TAP9:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(577, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields[] =
{
    /* RX_PF2_CTRL:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(669, 10, 8),
    /* RX_PF_CTRL:11:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(670, 14, 11)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields[] =
{
    /* RX_LMS_THRESH_SEL:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(668, 7, 0),
    /* RX_PHASE_THRESH_SEL:8:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(671, 14, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields[] =
{
    /* RX_PI_CNT_BIN_D:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(672, 7, 0),
    /* RX_PI_CNT_BIN_DQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(673, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields[] =
{
    /* RX_PI_CNT_BIN_L:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(676, 7, 0),
    /* RX_PI_CNT_BIN_LQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(677, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields[] =
{
    /* RX_PI_CNT_BIN_L_LD:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(678, 7, 0),
    /* RX_PI_CNT_BIN_D_LD:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(674, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields[] =
{
    /* RX_PI_CNT_BIN_P:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(679, 7, 0),
    /* RX_PI_CNT_BIN_PQ:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(680, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields[] =
{
    /* RX_PI_CNT_BIN_P_PD:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(681, 7, 0),
    /* RX_PI_CNT_BIN_D_PD:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(675, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_RX_PI_CTLr_fields[] =
{
    /* RX_PI_SLICERS_EN:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(686, 5, 0),
    /* RX_PI_PHASE_STEP_CNT:6:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(684, 8, 6),
    /* RX_PI_PHASE_STEP_DIR:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(685, 9, 9),
    /* RX_PI_MANUAL_MODE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(682, 10, 10),
    /* RX_PI_MANUAL_STROBE:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(683, 11, 11)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SCRATCHr_fields[] =
{
    /* UC_DSC_SCRATCH:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(824, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL0r_fields[] =
{
    /* EEE_MODE_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(308, 1, 1),
    /* EEE_QUIET_RX_AFE_PWRDWN_VAL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(312, 2, 2),
    /* IGNORE_RX_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(336, 3, 3),
    /* CL72_TIMER_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(218, 4, 4),
    /* UC_TUNE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(827, 5, 5),
    /* HW_TUNE_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(333, 6, 6),
    /* EEE_MEASURE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(307, 8, 8),
    /* UC_ACK_DSC_EEE_DONE:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(816, 11, 11),
    /* UC_ACK_DSC_RESTART:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(817, 13, 13),
    /* UC_ACK_DSC_CONFIG:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(815, 14, 14),
    /* SET_MEAS_INCOMPLETE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(693, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL1r_fields[] =
{
    /* RX_DSC_LOCK_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(666, 0, 0),
    /* RX_DSC_LOCK_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(667, 1, 1),
    /* DSC_CLR_FRC:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(293, 2, 2),
    /* DSC_CLR_FRC_VAL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(294, 3, 3),
    /* TRNSUM_FRZ_FRC:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(735, 4, 4),
    /* TRNSUM_FRZ_FRC_VAL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(736, 5, 5),
    /* TIMER_DONE_FRC:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(715, 6, 6),
    /* TIMER_DONE_FRC_VAL:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(716, 7, 7),
    /* FREQ_UPD_EN_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(328, 8, 8),
    /* FREQ_UPD_EN_FRC_VAL:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(329, 9, 9),
    /* CDR_FRZ_FRC:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(206, 10, 10),
    /* CDR_FRZ_FRC_VAL:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(207, 11, 11),
    /* TRNSUM_CLR_FRC:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(725, 12, 12),
    /* TRNSUM_CLR_FRC_VAL:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(726, 13, 13)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL2r_fields[] =
{
    /* EEE_LFSR_CNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(305, 12, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL3r_fields[] =
{
    /* MEASURE_LFSR_CNT:0:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(376, 12, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL4r_fields[] =
{
    /* ACQ_CDR_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(0, 4, 0),
    /* CDR_SETTLE_TIMEOUT:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(215, 9, 5),
    /* HW_TUNE_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(334, 14, 10)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL5r_fields[] =
{
    /* MEASURE_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(377, 4, 0),
    /* EEE_ACQ_CDR_TIMEOUT:5:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(301, 9, 5),
    /* EEE_CDR_SETTLE_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(303, 14, 10)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL6r_fields[] =
{
    /* EEE_HW_TUNE_TIMEOUT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(304, 4, 0),
    /* EEE_ANA_PWR_TIMEOUT:10:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(302, 14, 10)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL7r_fields[] =
{
    /* CDR_BWSEL_INTEG_ACQCDR:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(197, 3, 0),
    /* CDR_BWSEL_INTEG_EEE_ACQCDR:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(198, 7, 4),
    /* CDR_BWSEL_INTEG_NORM:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(199, 11, 8),
    /* CDR_BWSEL_PROP_ACQCDR:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(200, 12, 12),
    /* CDR_BWSEL_PROP_NORM:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(202, 14, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL8r_fields[] =
{
    /* PHASE_ERR_OFFSET:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(466, 3, 0),
    /* EEE_PHASE_ERR_OFFSET:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(309, 7, 4),
    /* PHASE_ERR_OFFSET_EN:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(467, 9, 8),
    /* EEE_PHASE_ERR_OFFSET_EN:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(310, 11, 10),
    /* CDR_BWSEL_PROP_EEE_ACQCDR:14:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(201, 14, 14)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_CTL9r_fields[] =
{
    /* RX_RESTART_PMD:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(688, 0, 0),
    /* RX_RESTART_PMD_HOLD:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(689, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr_fields[] =
{
    /* RX_DSC_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(665, 0, 0),
    /* MEAS_INCOMPLETE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(378, 1, 1),
    /* EEE_MEASURE_CNT:7:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(306, 15, 7)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr_fields[] =
{
    /* DSC_SM_SCRATCH:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(297, 3, 0),
    /* DSC_SM_READY_FOR_CMD:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(296, 4, 4),
    /* DSC_SM_GP_UC_REQ:5:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(295, 10, 5),
    /* DSC_STATE:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(298, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields[] =
{
    /* DSC_STATE_EEE_ONE_HOT:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(299, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields[] =
{
    /* DSC_STATE_ONE_HOT:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(300, 9, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr_fields[] =
{
    /* RESTART_PI_EXT_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(533, 0, 0),
    /* RESTART_SIGDET:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(535, 1, 1),
    /* RESTART_PMD_RESTART:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(534, 2, 2),
    /* EEE_QUIET_FROM_EEE_STATES:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(311, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUMr_fields[] =
{
    /* TRNSUM:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(719, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Ar_fields[] =
{
    /* TRNSUM_A:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(720, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr_fields[] =
{
    /* TRNSUM_A_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(721, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Br_fields[] =
{
    /* TRNSUM_B:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(722, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr_fields[] =
{
    /* TRNSUM_B_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(723, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Cr_fields[] =
{
    /* TRNSUM_C:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(724, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr_fields[] =
{
    /* TRNSUM_GAIN:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(737, 1, 0),
    /* TRNSUM_SEL_EMUX:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(745, 2, 2),
    /* TRNSUM_TAP_RANGE_SEL:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(747, 6, 4),
    /* TRNSUM_COR_SEL:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(727, 9, 8),
    /* TRNSUM_QPHASE_MULT_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(743, 12, 12),
    /* TRNSUM_RANDOM_TAPSEL_DISABLE:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(744, 13, 13),
    /* TRNSUM_EYE_CLOSURE_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(734, 14, 14),
    /* TRNSUM_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(732, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr_fields[] =
{
    /* TRNSUM_C_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(728, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_Dr_fields[] =
{
    /* TRNSUM_D:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(729, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr_fields[] =
{
    /* TRNSUM_D_LOW:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(730, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_LOr_fields[] =
{
    /* TRNSUM_LOW:6:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(739, 15, 6)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr_fields[] =
{
    /* TDT_PRBS_SLIP:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(711, 0, 0),
    /* CDR_1G_TRNSUM_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(196, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r_fields[] =
{
    /* TRNSUM_PATTERN:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(740, 9, 0),
    /* TRNSUM_PATTERN_FULL_CHECK_OFF:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(742, 12, 12),
    /* TRNSUM_EDGE_PATTERN_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(731, 14, 14),
    /* TRNSUM_INV_PATTERN_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(738, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r_fields[] =
{
    /* TRNSUM_PATTERN_BIT_EN:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(741, 9, 0)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr_fields[] =
{
    /* TRNSUM_TAP_EN:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(746, 7, 0),
    /* TRNSUM_TAP_SIGN:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(748, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr_fields[] =
{
    /* TDT_BIT_SEL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(707, 5, 0),
    /* TDT_PRBS_MODE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(710, 6, 6),
    /* TDT_TRNSUM_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(712, 7, 7),
    /* TDT_CYCLE_SEL:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(709, 11, 8),
    /* TDT_CYCLE_BIN:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(708, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_DSC_UC_CTLr_fields[] =
{
    /* UC_DSC_GP_UC_REQ:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(822, 5, 0),
    /* UC_DSC_ERROR_FOUND:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(821, 6, 6),
    /* UC_DSC_READY_FOR_CMD:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(823, 7, 7),
    /* UC_DSC_SUPP_INFO:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(825, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_DSC_VGA_CTL1r_fields[] =
{
    /* VGA_TIMER_T2:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(835, 2, 0),
    /* UC_TRNSUM_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(826, 3, 3),
    /* DC_OFFS_WRITE_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(284, 4, 4),
    /* VGA_DEC:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(833, 5, 5),
    /* VGA_INC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(834, 7, 7),
    /* RX_VGA_CTRL_VAL:8:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(691, 14, 8),
    /* VGA_WRITE:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(836, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr_fields[] =
{
    /* RX_DATA_THRESH_SEL:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(664, 6, 0),
    /* RX_VGA_CTRL:8:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(690, 14, 8)
};
static uint32_t BCMI_FALCON_XGXS_MDIO_AERr_fields[] =
{
    /* MDIO_AER:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(362, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr_fields[] =
{
    /* MDIO_BRCST_PORT_ADDR:0:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(364, 4, 0)
};
static uint32_t BCMI_FALCON_XGXS_MDIO_BLK_ADDRr_fields[] =
{
    /* MDIO_BLK_ADDR:4:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(363, 14, 4)
};
static uint32_t BCMI_FALCON_XGXS_MDIO_MASKDATAr_fields[] =
{
    /* MDIO_MASKDATA:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(373, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_MDIO_MMD_SELr_fields[] =
{
    /* MDIO_DEV_CL22_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(367, 0, 0),
    /* MDIO_DEV_PMD_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(371, 2, 2),
    /* MDIO_DEV_AN_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(366, 3, 3),
    /* MDIO_DEV_PHY_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(370, 4, 4),
    /* MDIO_DEV_DTE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(368, 5, 5),
    /* MDIO_DEV_PCS_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(369, 6, 6),
    /* MDIO_MULTI_MMDS_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(374, 14, 14),
    /* MDIO_MULTI_PRTS_EN:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(375, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ0r_fields[] =
{
    /* PATT_GEN_SEQ_0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(449, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ1r_fields[] =
{
    /* PATT_GEN_SEQ_1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(450, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ2r_fields[] =
{
    /* PATT_GEN_SEQ_2:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(456, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ3r_fields[] =
{
    /* PATT_GEN_SEQ_3:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(457, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ4r_fields[] =
{
    /* PATT_GEN_SEQ_4:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(458, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ5r_fields[] =
{
    /* PATT_GEN_SEQ_5:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(459, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ6r_fields[] =
{
    /* PATT_GEN_SEQ_6:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(460, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ7r_fields[] =
{
    /* PATT_GEN_SEQ_7:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(461, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ8r_fields[] =
{
    /* PATT_GEN_SEQ_8:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(462, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ9r_fields[] =
{
    /* PATT_GEN_SEQ_9:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(463, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r_fields[] =
{
    /* PATT_GEN_SEQ_10:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(451, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r_fields[] =
{
    /* PATT_GEN_SEQ_11:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(452, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r_fields[] =
{
    /* PATT_GEN_SEQ_12:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(453, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r_fields[] =
{
    /* PATT_GEN_SEQ_13:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(454, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r_fields[] =
{
    /* PATT_GEN_SEQ_14:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(455, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL0r_fields[] =
{
    /* VCO_STEP_TIME:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(832, 7, 0),
    /* VCO_START_TIME:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(831, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL1r_fields[] =
{
    /* RETRY_TIME:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(537, 7, 0),
    /* PRE_FREQ_DET_TIME:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(526, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL2r_fields[] =
{
    /* WIN_CAL_CNTR:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(837, 7, 0),
    /* RES_CAL_CNTR:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(536, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL3r_fields[] =
{
    /* FAST_SEARCH_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(320, 0, 0),
    /* CAP_CNT_MASK_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(178, 1, 1),
    /* CAP_SEQ_CYA:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(190, 2, 2),
    /* CAP_RESTART:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(185, 3, 3),
    /* CAP_RETRY_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(186, 4, 4),
    /* CAP_FORCE_SLOWDOWN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(181, 5, 5),
    /* CAP_FORCE_SLOWDOWN_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(182, 6, 6),
    /* CAP_SELECT_M_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(189, 7, 7),
    /* CAP_SELECT_M:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(188, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL4r_fields[] =
{
    /* PLL_LOCK_FRC_VAL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(478, 0, 0),
    /* PLL_LOCK_FRC:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(477, 1, 1),
    /* PLL_FORCE_CAP_PASS:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(471, 2, 2),
    /* PLL_FORCE_CAP_PASS_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(472, 3, 3),
    /* PLL_FORCE_CAP_DONE:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(469, 4, 4),
    /* PLL_FORCE_CAP_DONE_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(470, 5, 5),
    /* PLL_FORCE_FPASS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(475, 6, 6),
    /* PLL_FORCE_FDONE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(473, 7, 7),
    /* PLL_FORCE_FDONE_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(474, 8, 8),
    /* VCO_RST_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(830, 9, 9),
    /* SLOWDN_XOR:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(704, 10, 10),
    /* FREQ_MONITOR_EN:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(325, 11, 11),
    /* FREQ_DET_RESTART_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(321, 12, 12),
    /* FREQ_DET_RETRY_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(322, 13, 13),
    /* VCO_DONE_EN:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(828, 14, 14),
    /* PLL_SEQ_START:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(485, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL5r_fields[] =
{
    /* REFCLK_DIVCNT:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(528, 13, 0)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL6r_fields[] =
{
    /* REFCLK_DIVCNT_SEL:0:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(529, 2, 0)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL7r_fields[] =
{
    /* PLL_MODE:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(480, 3, 0),
    /* RESCAL_FRC_VAL:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(531, 7, 4),
    /* RESCAL_FRC:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(530, 8, 8),
    /* VCO_RANGE_ADJUST:9:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(829, 13, 9)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r_fields[] =
{
    /* PLL_LOCK_LH_LL:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(479, 0, 0),
    /* PLL_SEQ_PASS_LH_LL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(484, 1, 1),
    /* PLL_SEQ_DONE_LH_LL:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(482, 2, 2),
    /* FREQ_PASS_SM_LH_LL:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(327, 3, 3),
    /* FREQ_DONE_SM_LH_LL:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(324, 4, 4),
    /* CAP_PASS_LH_LL:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(184, 5, 5),
    /* CAP_DONE_LH_LL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(180, 6, 6),
    /* PLL_LOCK:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(476, 8, 8),
    /* PLL_SEQ_PASS:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(483, 9, 9),
    /* PLL_SEQ_DONE:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(481, 10, 10),
    /* FREQ_PASS_SM:11:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(326, 11, 11),
    /* FREQ_DONE_SM:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(323, 12, 12),
    /* CAP_PASS:13:13 */
    PHYMOD_SYMBOL_FIELD_ENCODE(183, 13, 13),
    /* CAP_DONE:14:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(179, 14, 14),
    /* LOST_PLL_LOCK_SM:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(357, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r_fields[] =
{
    /* CAP_SELECT:0:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(187, 7, 0),
    /* RESCAL_IN:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(532, 11, 8)
};
static uint32_t BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr_fields[] =
{
    /* DBG_SLOWDN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(275, 0, 0),
    /* DBG_SLOWDN_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(276, 1, 1),
    /* DBG_FDBCK:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(272, 2, 2),
    /* DBG_CAP_STATE_ONE_HOT:3:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(271, 7, 3),
    /* DBG_PLL_STATE_ONE_HOT:8:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(274, 15, 8)
};
static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL0r_fields[] =
{
    /* SIGNAL_DETECT_FILTER_COUNT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(698, 4, 0),
    /* LOS_FILTER_COUNT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(358, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL1r_fields[] =
{
    /* AFE_SIGNAL_DETECT_DIS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(9, 0, 0),
    /* EXT_LOS_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(318, 1, 1),
    /* EXT_LOS_INV:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(319, 2, 2),
    /* IGNORE_LP_MODE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(335, 3, 3),
    /* SIGNAL_DETECT_FILTER_1US:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(697, 4, 4),
    /* ENERGY_DETECT_FRC:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(315, 5, 5),
    /* ENERGY_DETECT_FRC_VAL:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(316, 6, 6),
    /* SIGNAL_DETECT_FRC:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(699, 7, 7),
    /* SIGNAL_DETECT_FRC_VAL:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(700, 8, 8),
    /* ENERGY_DETECT_MASK_COUNT:11:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(317, 15, 11)
};
static uint32_t BCMI_FALCON_XGXS_SIGDET_CTL2r_fields[] =
{
    /* LOS_THRESH:0:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(359, 2, 0),
    /* SIGNAL_DETECT_THRESH:4:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(703, 6, 4),
    /* HOLD_LOS_COUNT:8:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(331, 10, 8),
    /* HOLD_SD_COUNT:11:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(332, 13, 11)
};
static uint32_t BCMI_FALCON_XGXS_SIGDET_STS0r_fields[] =
{
    /* SIGNAL_DETECT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(695, 0, 0),
    /* SIGNAL_DETECT_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(696, 1, 1),
    /* ENERGY_DETECT:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(313, 2, 2),
    /* ENERGY_DETECT_CHANGE:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(314, 3, 3),
    /* SIGNAL_DETECT_RAW:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(701, 4, 4),
    /* SIGNAL_DETECT_RAW_CHANGE:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(702, 5, 5),
    /* AFE_SIGDET_THRESH:8:10 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(8, 10, 8)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr_fields[] =
{
    /* DIG_LPBK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(287, 0, 0),
    /* DIG_LPBK_PD_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(291, 1, 1),
    /* DIG_LPBK_PD_BIAS_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(288, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields[] =
{
    /* DIG_LPBK_PD_LATE_IND:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(290, 0, 0),
    /* DIG_LPBK_PD_EARLY_IND:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(289, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields[] =
{
    /* MAX_PRBS_BURST_ERR_LENGTH_STATUS:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(360, 5, 0)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr_fields[] =
{
    /* RX_PMD_DP_INVERT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(687, 0, 0),
    /* DBG_MASK_DIG_LPBK_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(273, 2, 2),
    /* TLB_RX_DIFF_DEC_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(717, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields[] =
{
    /* PMD_RX_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(496, 0, 0),
    /* PMD_RX_LOCK_CHANGE:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(497, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields[] =
{
    /* PRBS_BURST_ERR_LENGTH_STATUS:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(501, 5, 0)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr_fields[] =
{
    /* PRBS_CHK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(504, 0, 0),
    /* PRBS_CHK_MODE_SEL:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(516, 3, 1),
    /* PRBS_CHK_INV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(511, 4, 4),
    /* PRBS_CHK_MODE:5:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(515, 6, 5),
    /* PRBS_CHK_EN_AUTO_MODE:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(505, 7, 7),
    /* PRBS_BURST_LEN_CHK_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(502, 8, 8),
    /* PRBS_CHK_ERR_CNT_BURST_MODE:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(508, 9, 9),
    /* TRNSUM_ERROR_COUNT_EN:10:10 */
    PHYMOD_SYMBOL_FIELD_ENCODE(733, 10, 10),
    /* PRBS_CHK_CLK_EN_FRC_ON:11:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(503, 11, 11)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields[] =
{
    /* PRBS_CHK_LOCK_CNT:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(513, 4, 0),
    /* PRBS_CHK_OOL_CNT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(517, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields[] =
{
    /* PRBS_CHK_EN_TIMER_MODE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(507, 1, 0),
    /* PRBS_CHK_EN_TIMEOUT:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(506, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields[] =
{
    /* PRBS_CHK_ERR_CNT_LSB:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(509, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields[] =
{
    /* PRBS_CHK_ERR_CNT_MSB:0:14 */
    PHYMOD_SYMBOL_FIELD_ENCODE(510, 14, 0),
    /* PRBS_CHK_LOCK_LOST_LH:15:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(514, 15, 15)
};
static uint32_t BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields[] =
{
    /* PRBS_CHK_LOCK:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(512, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr_fields[] =
{
    /* TX_PMD_DP_INVERT:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(809, 0, 0),
    /* TX_PCS_NATIVE_ANA_FRMT_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(778, 1, 1),
    /* TX_MUX_SEL_ORDER:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(777, 2, 2),
    /* TLB_TX_DIFF_ENC_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(718, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr_fields[] =
{
    /* PATT_GEN_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(448, 0, 0),
    /* PATT_GEN_STOP_POS:8:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(465, 11, 8),
    /* PATT_GEN_START_POS:12:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(464, 15, 12)
};
static uint32_t BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr_fields[] =
{
    /* PRBS_GEN_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(518, 0, 0),
    /* PRBS_GEN_MODE_SEL:1:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(521, 3, 1),
    /* PRBS_GEN_INV:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(520, 4, 4),
    /* PRBS_GEN_ERR_INS:5:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(519, 5, 5)
};
static uint32_t BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr_fields[] =
{
    /* RMT_LPBK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(551, 0, 0),
    /* RMT_LPBK_PD_MODE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(555, 1, 1),
    /* RMT_LPBK_PD_FRC_ON:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(553, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields[] =
{
    /* RMT_LPBK_PD_LATE_IND:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(554, 0, 0),
    /* RMT_LPBK_PD_EARLY_IND:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(552, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL0r_fields[] =
{
    /* TXFIR_PRE_OFFSET:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(768, 3, 0),
    /* TXFIR_MAIN_OFFSET:4:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(756, 7, 4),
    /* TXFIR_POST_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(765, 11, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL1r_fields[] =
{
    /* TXFIR_POST2:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(757, 4, 0),
    /* TXFIR_POST2_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(759, 11, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_CTL2r_fields[] =
{
    /* TXFIR_POST3:0:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(760, 3, 0),
    /* TXFIR_POST3_OFFSET:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(762, 11, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r_fields[] =
{
    /* SDK_TX_DISABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(692, 0, 0),
    /* PMD_TX_DISABLE_PIN_DIS:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(500, 1, 1),
    /* TX_DISABLE_TIMER_CTRL:2:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(770, 7, 2),
    /* TX_EEE_QUIET_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(772, 8, 8),
    /* TX_EEE_ALERT_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(771, 9, 9),
    /* TX_DISABLE_OUTPUT_SEL:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(769, 11, 10),
    /* DP_RESET_TX_DISABLE_DIS:12:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(292, 12, 12)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_STS0r_fields[] =
{
    /* TXFIR_PRE_AFTER_OVR:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(767, 4, 0),
    /* TXFIR_POST_AFTER_OVR:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(764, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_STS1r_fields[] =
{
    /* TXFIR_MAIN_AFTER_OVR:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(755, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_STS2r_fields[] =
{
    /* TXFIR_PRE_ADJUSTED:0:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(766, 4, 0),
    /* TXFIR_POST_ADJUSTED:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(763, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_STS3r_fields[] =
{
    /* TXFIR_MAIN_ADJUSTED:0:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(754, 6, 0),
    /* TXFIR_POST2_ADJUSTED:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(758, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_STS4r_fields[] =
{
    /* TXFIR_POST3_ADJUSTED:0:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(761, 3, 0)
};
static uint32_t BCMI_FALCON_XGXS_TXFIR_UC_CTL0r_fields[] =
{
    /* MICRO_TX_DISABLE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(441, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_CTL0r_fields[] =
{
    /* TXCOM_POST_TAP_ALERT_VAL:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(752, 5, 0),
    /* TXCOM_PRE_TAP_ALERT_VAL:8:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(753, 12, 8)
};
static uint32_t BCMI_FALCON_XGXS_TX_CTL1r_fields[] =
{
    /* TXCOM_MAIN_TAP_ALERT_VAL:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(751, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_CTL2r_fields[] =
{
    /* TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(749, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_CTL3r_fields[] =
{
    /* TXCOM_CL93N72_WAIT_CNTR_LIMIT:0:8 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(750, 8, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r_fields[] =
{
    /* TX_PI_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(779, 0, 0),
    /* TX_PI_JITTER_FILTER_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(790, 1, 1),
    /* TX_PI_EXT_CTRL_EN:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(780, 2, 2),
    /* TX_PI_FREQ_OVERRIDE_EN:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(783, 3, 3),
    /* TX_PI_SJ_GEN_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(807, 4, 4),
    /* TX_PI_SSC_GEN_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(808, 5, 5),
    /* TX_PI_JIT_SSC_FREQ_MODE:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(793, 6, 6),
    /* TX_PI_SECOND_ORDER_LOOP_EN:7:7 */
    PHYMOD_SYMBOL_FIELD_ENCODE(806, 7, 7),
    /* TX_PI_FIRST_ORDER_BWSEL_INTEG:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(782, 9, 8),
    /* TX_PI_SECOND_ORDER_BWSEL_INTEG:10:11 */
    PHYMOD_SYMBOL_FIELD_ENCODE(805, 11, 10),
    /* TX_PI_EXT_PHASE_BWSEL_INTEG:12:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(781, 14, 12)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r_fields[] =
{
    /* TX_PI_FREQ_OVERRIDE_VAL:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(784, 14, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r_fields[] =
{
    /* TX_PI_JIT_FREQ_IDX:0:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(792, 5, 0),
    /* TX_PI_JIT_AMP:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(791, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r_fields[] =
{
    /* TX_PI_PHASE_OVERRIDE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(799, 0, 0),
    /* TX_PI_PHASE_STROBE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(802, 1, 1),
    /* TX_PI_PHASE_STEP_DIR:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(800, 2, 2),
    /* TX_PI_PHASE_INVERT:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(798, 4, 4),
    /* TX_PI_PHASE_STEP_NUM:8:11 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(801, 11, 8)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r_fields[] =
{
    /* TX_PI_FRZ_FRC:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(785, 0, 0),
    /* TX_PI_FRZ_FRC_VAL:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(786, 1, 1),
    /* TX_PI_FRZ_MODE:2:2 */
    PHYMOD_SYMBOL_FIELD_ENCODE(787, 2, 2),
    /* TX_PI_RESET_CODE_DBG:3:3 */
    PHYMOD_SYMBOL_FIELD_ENCODE(803, 3, 3),
    /* TX_PI_RMT_LPBK_BYPASS_FLT:4:4 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(804, 4, 4)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS0r_fields[] =
{
    /* TX_PI_PHASE_CNTR:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(796, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS1r_fields[] =
{
    /* TX_PI_INTEG1_REG:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(788, 13, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS2r_fields[] =
{
    /* TX_PI_INTEG2_REG:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(789, 14, 0)
};
static uint32_t BCMI_FALCON_XGXS_TX_PI_PMD_STS3r_fields[] =
{
    /* TX_PI_PHASE_ERR:0:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(797, 5, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_CTL0r_fields[] =
{
    /* MICRO_RA_WRDATASIZE:0:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(418, 1, 0),
    /* MICRO_RA_RDDATASIZE:4:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(413, 5, 4),
    /* MICRO_RA_INIT:8:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(409, 9, 8),
    /* MICRO_AUTOINC_WRADDR_EN:12:12 */
    PHYMOD_SYMBOL_FIELD_ENCODE(380, 12, 12),
    /* MICRO_AUTOINC_RDADDR_EN:13:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(379, 13, 13)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr_fields[] =
{
    /* MICRO_RA_RDADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(411, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr_fields[] =
{
    /* MICRO_RA_RDADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(412, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr_fields[] =
{
    /* MICRO_RA_RDDATA_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(414, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr_fields[] =
{
    /* MICRO_RA_RDDATA_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(415, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_STS0r_fields[] =
{
    /* MICRO_RA_INITDONE:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(410, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr_fields[] =
{
    /* MICRO_RA_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(416, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr_fields[] =
{
    /* MICRO_RA_WRADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(417, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr_fields[] =
{
    /* MICRO_RA_WRDATA_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(419, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr_fields[] =
{
    /* MICRO_RA_WRDATA_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(420, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_CLK_CTL0r_fields[] =
{
    /* MICRO_MASTER_CLK_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(394, 0, 0),
    /* MICRO_CORE_CLK_EN:1:1 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(383, 1, 1)
};
static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields[] =
{
    /* MICRO_RA_ECC_WRDATA:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(408, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r_fields[] =
{
    /* MICRO_ECCG_MODE:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(387, 0, 0),
    /* MICRO_ECC_FRC_DISABLE:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(389, 1, 1),
    /* MICRO_ECC_CORRUPT:4:5 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(388, 5, 4)
};
static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r_fields[] =
{
    /* MICRO_CODE_RAM_ECC_ADDRESS:0:14 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(381, 14, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r_fields[] =
{
    /* MICRO_RA_ECC_RDDATA:0:6 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(407, 6, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields[] =
{
    /* MICRO_CODE_RAM_TM:0:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(382, 13, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields[] =
{
    /* MICRO_PRAMIF_AHB_WRADDR_LSW:2:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(396, 15, 2)
};
static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields[] =
{
    /* MICRO_PRAMIF_AHB_WRADDR_MSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(397, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r_fields[] =
{
    /* MICRO_PRAMIF_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(398, 0, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_PVT_STS0r_fields[] =
{
    /* MICRO_PVT_TEMPDATA_RMI:0:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(404, 9, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RAM_CTL0r_fields[] =
{
    /* MICRO_DR_LOOKTAB_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(385, 0, 0),
    /* MICRO_DR_SIZE:8:13 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(386, 13, 8)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r_fields[] =
{
    /* MICRO_M0_HRESP_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(393, 0, 0),
    /* MICRO_SW_PMI_HP_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(438, 1, 1),
    /* MICRO_SW_PMI_HP_EXT_RSTB:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(437, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r_fields[] =
{
    /* MICRO_M0_DEFAULT_SLAVE_ERROR:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(392, 0, 0),
    /* MICRO_RMI_DEFAULT_SLAVE_ERROR:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(421, 1, 1),
    /* MICRO_PR_DEFAULT_SLAVE_ERROR:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(401, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r_fields[] =
{
    /* MICRO_RMI_MBOX_MSGOUT_INTR_EN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(432, 0, 0),
    /* MICRO_RMI_ECC_CORR_ERR_INTR_EN:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(422, 4, 4),
    /* MICRO_RMI_ECC_UNCORR_ERR_INTR_EN:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(426, 5, 5),
    /* MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(424, 6, 6),
    /* MICRO_RMI_M0_LOCKUP_INTR_EN:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(428, 8, 8),
    /* MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(430, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r_fields[] =
{
    /* MICRO_RMI_MBOX_MSGOUT_STATUS:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(433, 0, 0),
    /* MICRO_RMI_ECC_CORR_ERR_STATUS:4:4 */
    PHYMOD_SYMBOL_FIELD_ENCODE(423, 4, 4),
    /* MICRO_RMI_ECC_UNCORR_ERR_STATUS:5:5 */
    PHYMOD_SYMBOL_FIELD_ENCODE(427, 5, 5),
    /* MICRO_RMI_ECC_MULTIROW_ERR_STATUS:6:6 */
    PHYMOD_SYMBOL_FIELD_ENCODE(425, 6, 6),
    /* MICRO_RMI_M0_LOCKUP_STATUS:8:8 */
    PHYMOD_SYMBOL_FIELD_ENCODE(429, 8, 8),
    /* MICRO_RMI_M0_SYSTEMRESETREQ_STATUS:9:9 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(431, 9, 9)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r_fields[] =
{
    /* MICRO_RMI_MBOX_SEND_MSGIN:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(434, 0, 0),
    /* MICRO_GEN_INTR_RMI_MBOX0WR:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(390, 1, 1),
    /* MICRO_GEN_INTR_RMI_MBOX1WR:2:2 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(391, 2, 2)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields[] =
{
    /* MICRO_PR_AUTOINC_NXT_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(400, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r_fields[] =
{
    /* MICRO_PVT_TEMPDATA_FRCVAL:0:9 */
    PHYMOD_SYMBOL_FIELD_ENCODE(403, 9, 0),
    /* MICRO_PVT_TEMPDATA_FRC:12:12 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(402, 12, 12)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields[] =
{
    /* MICRO_RA_AUTOINC_NXT_RDADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(405, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields[] =
{
    /* MICRO_RA_AUTOINC_NXT_WRADDR_LSW:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(406, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r_fields[] =
{
    /* MICRO_RMI_TO_MICRO_MBOX0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(435, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r_fields[] =
{
    /* MICRO_RMI_TO_MICRO_MBOX1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(436, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_RST_CTL0r_fields[] =
{
    /* MICRO_MASTER_RSTB:0:0 */
    PHYMOD_SYMBOL_FIELD_ENCODE(395, 0, 0),
    /* MICRO_CORE_RSTB:1:1 */
    PHYMOD_SYMBOL_FIELD_ENCODE(384, 1, 1),
    /* MICRO_PRAM_IF_RSTB:3:3 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(399, 3, 3)
};
static uint32_t BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r_fields[] =
{
    /* MICRO_TO_RMI_MBOX0:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(439, 15, 0)
};
static uint32_t BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r_fields[] =
{
    /* MICRO_TO_RMI_MBOX1:0:15 */
    PHYMOD_SYMBOL_FIELD_FLAG_LAST | PHYMOD_SYMBOL_FIELD_ENCODE(440, 15, 0)
};



/*******************************************************************************
 *
 * The following is the field name table.
 */
#if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_NAMES_BCMI_FALCON_XGXS
const char* bcmi_falcon_xgxs_fields[] = 
{
    "ACQ_CDR_TIMEOUT",
    "AFE_RX_PWRDN_FRC",
    "AFE_RX_PWRDN_FRC_VAL",
    "AFE_RX_RCLK20_PWRDN_FRC",
    "AFE_RX_RCLK20_PWRDN_FRC_VAL",
    "AFE_RX_RESET_FRC",
    "AFE_RX_RESET_FRC_VAL",
    "AFE_SIGDET_PWRDN",
    "AFE_SIGDET_THRESH",
    "AFE_SIGNAL_DETECT_DIS",
    "AFE_S_PLL_PWRDN",
    "AFE_S_PLL_RESET_FRC",
    "AFE_S_PLL_RESET_FRC_VAL",
    "AFE_TX_PWRDN_FRC",
    "AFE_TX_PWRDN_FRC_VAL",
    "AFE_TX_RESET_FRC",
    "AFE_TX_RESET_FRC_VAL",
    "AMS_PLL_BGINT",
    "AMS_PLL_BGIP",
    "AMS_PLL_BGR_CTATADJ",
    "AMS_PLL_BGR_PTATADJ",
    "AMS_PLL_CAL_AUX",
    "AMS_PLL_CAL_OFF",
    "AMS_PLL_COMP_VTH",
    "AMS_PLL_DRV_HV_DISABLE",
    "AMS_PLL_ENABLE_FTUNE",
    "AMS_PLL_EN_HRZ",
    "AMS_PLL_FORCE_KVH_BW",
    "AMS_PLL_FORCE_RESCAL",
    "AMS_PLL_IMAX_IBIAS",
    "AMS_PLL_IMAX_ICK",
    "AMS_PLL_IMAX_ICKGEN",
    "AMS_PLL_IMAX_ICLKIDRV1",
    "AMS_PLL_IMAX_ICLKINT",
    "AMS_PLL_IMAX_ICLKODRV1",
    "AMS_PLL_IMAX_ICMLDIV",
    "AMS_PLL_IMAX_ICOMP",
    "AMS_PLL_IMAX_ICP",
    "AMS_PLL_IMAX_IOP",
    "AMS_PLL_IMAX_IRXCLKBUF",
    "AMS_PLL_IMIN_IBIAS",
    "AMS_PLL_IMIN_ICK",
    "AMS_PLL_IMIN_ICKGEN",
    "AMS_PLL_IMIN_ICLKIDRV1",
    "AMS_PLL_IMIN_ICLKINT",
    "AMS_PLL_IMIN_ICLKODRV1",
    "AMS_PLL_IMIN_ICMLDIV",
    "AMS_PLL_IMIN_ICOMP",
    "AMS_PLL_IMIN_ICP",
    "AMS_PLL_IMIN_IOP",
    "AMS_PLL_IMIN_IRXCLKBUF",
    "AMS_PLL_IMODE_IBIAS",
    "AMS_PLL_IMODE_ICK",
    "AMS_PLL_IMODE_ICKGEN",
    "AMS_PLL_IMODE_ICLKIDRV1",
    "AMS_PLL_IMODE_ICLKINT",
    "AMS_PLL_IMODE_ICLKODRV1",
    "AMS_PLL_IMODE_ICMLDIV",
    "AMS_PLL_IMODE_ICOMP",
    "AMS_PLL_IMODE_ICP",
    "AMS_PLL_IMODE_IOP",
    "AMS_PLL_IMODE_IRXCLKBUF",
    "AMS_PLL_IQP",
    "AMS_PLL_IVCO",
    "AMS_PLL_KVH_FORCE",
    "AMS_PLL_MIX1P2CR_CTATADJ",
    "AMS_PLL_MIX1P2CR_PTATADJ",
    "AMS_PLL_MIX3P1CR_CTATADJ",
    "AMS_PLL_MIX3P1CR_PTATADJ",
    "AMS_PLL_MIX3P1C_CALR_CTATADJ",
    "AMS_PLL_MIX3P1C_CALR_PTATADJ",
    "AMS_PLL_PLL2RX_CLKBW",
    "AMS_PLL_REFH_PLL",
    "AMS_PLL_REFL_PLL",
    "AMS_PLL_RESET",
    "AMS_PLL_SET_CLK4TSC",
    "AMS_PLL_SPARE_101_96",
    "AMS_PLL_SPARE_117_112",
    "AMS_PLL_SPARE_23_22",
    "AMS_PLL_STS",
    "AMS_PLL_TEST_BG_OPAMP_BIAS",
    "AMS_PLL_TEST_PLL",
    "AMS_PLL_TEST_PNP",
    "AMS_PLL_TEST_PORT_MAX_AMPLITUDE",
    "AMS_PLL_TEST_RX",
    "AMS_PLL_TEST_VC",
    "AMS_PLL_TEST_VREF",
    "AMS_PLL_VBYPASS",
    "AMS_PLL_VCOICTRL",
    "AMS_PLL_VCO_INDICATOR",
    "AMS_PLL_VDDR_BGB",
    "AMS_RX_CLK_BW_CTRL",
    "AMS_RX_CM_VOLTAGE_IBIAS",
    "AMS_RX_D2C_CLKBUF_IBIAS",
    "AMS_RX_DAC4CK_DAT",
    "AMS_RX_DAC4CK_LMS",
    "AMS_RX_DAC4CK_PHS",
    "AMS_RX_DC_COUPLE",
    "AMS_RX_DC_OFFSET",
    "AMS_RX_DC_OFFSET_RANGE",
    "AMS_RX_DFE_HGAIN_EN",
    "AMS_RX_DFE_SLICER_CAL_IBIAS",
    "AMS_RX_DFE_SLICER_IBIAS",
    "AMS_RX_DFE_SUM_BUF_IBIAS",
    "AMS_RX_DFE_TAP_WEIGHT_IBIAS",
    "AMS_RX_DLL_IBIAS",
    "AMS_RX_EN_TAP9DELAY",
    "AMS_RX_EQ_LZ_EN",
    "AMS_RX_FORCE_DC_OFFSET",
    "AMS_RX_MASTER_DIODES_IBIAS",
    "AMS_RX_MET_R_IBIAS",
    "AMS_RX_OFFSET_CORRECTION_IBIAS",
    "AMS_RX_OFFSET_CORRECTION_RESCAL_MUX",
    "AMS_RX_PD_CH_P1",
    "AMS_RX_PEAKING_FILTER_IBIAS",
    "AMS_RX_PEAKING_FILTER_RESCAL_MUX",
    "AMS_RX_PHASE_INTERPOLATORS_IBIAS",
    "AMS_RX_PWRDN_FTAP",
    "AMS_RX_RX_OFFSET_PD",
    "AMS_RX_SEL_D2CLP",
    "AMS_RX_SEL_TH4DFE",
    "AMS_RX_SEL_UGBW",
    "AMS_RX_SHORT_VGA_OUTPUT",
    "AMS_RX_SIGDET_BYPASS",
    "AMS_RX_SIGDET_IBIAS",
    "AMS_RX_SIGDET_POWER_SAVE",
    "AMS_RX_SIGDET_PWRDN",
    "AMS_RX_SIGDET_THRESHOLD",
    "AMS_RX_SPARE_111_104",
    "AMS_RX_SPARE_123",
    "AMS_RX_SPARE_135_134",
    "AMS_RX_SPARE_143_142",
    "AMS_RX_SPARE_151_150",
    "AMS_RX_SPARE_159",
    "AMS_RX_SPARE_16",
    "AMS_RX_SPARE_63",
    "AMS_RX_SPARE_95",
    "AMS_RX_STS",
    "AMS_RX_TBD_IBIAS",
    "AMS_RX_TERMINATION_RESISTOR_RESCAL_MUX",
    "AMS_RX_TPORT_EN",
    "AMS_RX_VGA0_IBIAS",
    "AMS_RX_VGA0_RESCAL_MUX",
    "AMS_RX_VGA1_IBIAS",
    "AMS_RX_VGA1_RESCAL_MUX",
    "AMS_RX_VGA2_IBIAS",
    "AMS_RX_VGA2_RESCAL_MUX",
    "AMS_RX_VGA3_IBIAS",
    "AMS_RX_VGA3_RESCAL_MUX",
    "AMS_RX_VGA_10G_BW",
    "AMS_RX_VGA_LOW_GAIN",
    "AMS_RX_VGA_STEP_MODE",
    "AMS_TX_AMP_CTL",
    "AMS_TX_CAL_AUX",
    "AMS_TX_CAL_OFF",
    "AMS_TX_DCC_DIS",
    "AMS_TX_DCC_SEL",
    "AMS_TX_DRIVERMODE",
    "AMS_TX_ELEC_IDLE_AUX",
    "AMS_TX_IBIAS",
    "AMS_TX_ICML",
    "AMS_TX_ILDO",
    "AMS_TX_LDO_VREF",
    "AMS_TX_POST2_COEF",
    "AMS_TX_POST3_COEF",
    "AMS_TX_SEL_EMPH_MODE",
    "AMS_TX_SIGN_POST2",
    "AMS_TX_SIGN_POST3",
    "AMS_TX_SPARE_0",
    "AMS_TX_SPARE_21_19",
    "AMS_TX_SPARE_31",
    "AMS_TX_SPARE_3_1",
    "AMS_TX_SPARE_63_48",
    "AMS_TX_STS",
    "AMS_TX_TEST_DATA",
    "AMS_TX_TICKSEL",
    "AMS_TX_VDDR_BGB",
    "BR_PD_EN",
    "CAP_CNT_MASK_EN",
    "CAP_DONE",
    "CAP_DONE_LH_LL",
    "CAP_FORCE_SLOWDOWN",
    "CAP_FORCE_SLOWDOWN_EN",
    "CAP_PASS",
    "CAP_PASS_LH_LL",
    "CAP_RESTART",
    "CAP_RETRY_EN",
    "CAP_SELECT",
    "CAP_SELECT_M",
    "CAP_SELECT_M_EN",
    "CAP_SEQ_CYA",
    "CDR_1G_FORCE_EN",
    "CDR_1G_MANUAL_MODE",
    "CDR_1G_MANUAL_STROBE",
    "CDR_1G_PHASE_POINTER",
    "CDR_1G_SWAP_PZ",
    "CDR_1G_TRNSUM_EN",
    "CDR_BWSEL_INTEG_ACQCDR",
    "CDR_BWSEL_INTEG_EEE_ACQCDR",
    "CDR_BWSEL_INTEG_NORM",
    "CDR_BWSEL_PROP_ACQCDR",
    "CDR_BWSEL_PROP_EEE_ACQCDR",
    "CDR_BWSEL_PROP_NORM",
    "CDR_FREQ_EN",
    "CDR_FREQ_OVERRIDE_EN",
    "CDR_FREQ_OVERRIDE_VAL",
    "CDR_FRZ_FRC",
    "CDR_FRZ_FRC_VAL",
    "CDR_INTEG_REG",
    "CDR_INTEG_REG_CLR",
    "CDR_INTEG_SAT_SEL",
    "CDR_LM_OUTOFLOCK",
    "CDR_LM_THR_SEL",
    "CDR_PHASE_ERROR",
    "CDR_PHASE_ERR_FRZ",
    "CDR_SETTLE_TIMEOUT",
    "CDR_VCO_REG",
    "CDR_ZERO_POLARITY",
    "CL72_TIMER_EN",
    "CL93N72_BAD_MARKER_CNT",
    "CL93N72_BRK_RING_OSC",
    "CL93N72_CL93PRBSSEED_ORDER",
    "CL93N72_CL93PRBSSEED_RANDOM",
    "CL93N72_CTRL_FRAME_DLY",
    "CL93N72_DIS_MAX_WAIT_TIMER",
    "CL93N72_DME_CELL_BOUNDARY_CHK",
    "CL93N72_FRAME_CONSISTENCY_CHK_EN",
    "CL93N72_FRAME_LOCK",
    "CL93N72_GOOD_MARKER_CNT",
    "CL93N72_IEEE_FRAME_LOCK",
    "CL93N72_IEEE_LD_COEFF_UPDATE",
    "CL93N72_IEEE_LD_STATUS_REPORT",
    "CL93N72_IEEE_LP_COEFF_UPDATE",
    "CL93N72_IEEE_LP_STATUS_REPORT",
    "CL93N72_IEEE_RECEIVER_STATUS",
    "CL93N72_IEEE_RESTART_TRAINING",
    "CL93N72_IEEE_TRAINING_ENABLE",
    "CL93N72_IEEE_TRAINING_FAILURE",
    "CL93N72_IEEE_TRAINING_STATUS",
    "CL93N72_LD_XMT_STATUS_PAGE",
    "CL93N72_LOCAL_RX_READY",
    "CL93N72_MICRO_FRAME_LOCK_INT_EN",
    "CL93N72_MICRO_FRAME_LOCK_LSTATUS",
    "CL93N72_MICRO_STATUS_CHG_INT_EN",
    "CL93N72_MICRO_STATUS_CHG_LSTATUS",
    "CL93N72_MICRO_UPDATE_CHG_INT_EN",
    "CL93N72_MICRO_UPDATE_CHG_LSTATUS",
    "CL93N72_PPM_OFFSET_EN",
    "CL93N72_PRBS_SEL",
    "CL93N72_RX_DP_LN_CLK_EN",
    "CL93N72_RX_SIGNAL_OK",
    "CL93N72_RX_TRAINING_EN",
    "CL93N72_STRICT_DME_CHK",
    "CL93N72_STRICT_MARKER_CHK",
    "CL93N72_SW_FRAME_LOCK",
    "CL93N72_SW_REMOTE_RX_READY",
    "CL93N72_SW_RX_TRAINED",
    "CL93N72_TRAINING_FSM_SIGNAL_DETECT",
    "CL93N72_TR_COARSE_LOCK",
    "CL93N72_TXFIR_MAIN",
    "CL93N72_TXFIR_POST",
    "CL93N72_TXFIR_PRE",
    "CL93N72_TX_DP_LN_CLK_EN",
    "CL93N72_XMT_UPDATE_PAGE",
    "CORE_DP_RESET_STATE",
    "CORE_DP_S_RSTB",
    "CORE_MULTICAST_MASK_CONTROL",
    "CORE_REG_RESET_OCCURRED",
    "CORE_S_RSTB",
    "DATA_THRESH_SEL_VAL",
    "DATA_THRESH_WRITE",
    "DBG_CAP_STATE_ONE_HOT",
    "DBG_FDBCK",
    "DBG_MASK_DIG_LPBK_EN",
    "DBG_PLL_STATE_ONE_HOT",
    "DBG_SLOWDN",
    "DBG_SLOWDN_CHANGE",
    "DC_OFFSET_BIN",
    "DC_OFFS_ACC_CLR",
    "DC_OFFS_EN",
    "DC_OFFS_GAIN",
    "DC_OFFS_GRADIENT_INVERT",
    "DC_OFFS_HYS_EN",
    "DC_OFFS_HYS_MAG",
    "DC_OFFS_WRITE_EN",
    "DC_OFFS_WRITE_FRC_EN",
    "DC_OFFS_WRITE_VAL",
    "DIG_LPBK_EN",
    "DIG_LPBK_PD_BIAS_EN",
    "DIG_LPBK_PD_EARLY_IND",
    "DIG_LPBK_PD_LATE_IND",
    "DIG_LPBK_PD_MODE",
    "DP_RESET_TX_DISABLE_DIS",
    "DSC_CLR_FRC",
    "DSC_CLR_FRC_VAL",
    "DSC_SM_GP_UC_REQ",
    "DSC_SM_READY_FOR_CMD",
    "DSC_SM_SCRATCH",
    "DSC_STATE",
    "DSC_STATE_EEE_ONE_HOT",
    "DSC_STATE_ONE_HOT",
    "EEE_ACQ_CDR_TIMEOUT",
    "EEE_ANA_PWR_TIMEOUT",
    "EEE_CDR_SETTLE_TIMEOUT",
    "EEE_HW_TUNE_TIMEOUT",
    "EEE_LFSR_CNT",
    "EEE_MEASURE_CNT",
    "EEE_MEASURE_EN",
    "EEE_MODE_EN",
    "EEE_PHASE_ERR_OFFSET",
    "EEE_PHASE_ERR_OFFSET_EN",
    "EEE_QUIET_FROM_EEE_STATES",
    "EEE_QUIET_RX_AFE_PWRDWN_VAL",
    "ENERGY_DETECT",
    "ENERGY_DETECT_CHANGE",
    "ENERGY_DETECT_FRC",
    "ENERGY_DETECT_FRC_VAL",
    "ENERGY_DETECT_MASK_COUNT",
    "EXT_LOS_EN",
    "EXT_LOS_INV",
    "FAST_SEARCH_MODE",
    "FREQ_DET_RESTART_EN",
    "FREQ_DET_RETRY_EN",
    "FREQ_DONE_SM",
    "FREQ_DONE_SM_LH_LL",
    "FREQ_MONITOR_EN",
    "FREQ_PASS_SM",
    "FREQ_PASS_SM_LH_LL",
    "FREQ_UPD_EN_FRC",
    "FREQ_UPD_EN_FRC_VAL",
    "HEARTBEAT_COUNT_1US",
    "HOLD_LOS_COUNT",
    "HOLD_SD_COUNT",
    "HW_TUNE_EN",
    "HW_TUNE_TIMEOUT",
    "IGNORE_LP_MODE",
    "IGNORE_RX_MODE",
    "LANE_ADDR_0",
    "LANE_ADDR_1",
    "LANE_ADDR_2",
    "LANE_ADDR_3",
    "LANE_DP_RESET_STATE",
    "LANE_MULTICAST_MASK_CONTROL",
    "LANE_REG_RESET_OCCURRED",
    "LANE_RESET_RELEASED",
    "LANE_RESET_RELEASED_INDEX",
    "LN_DP_S_RSTB",
    "LN_RX_DP_S_RSTB",
    "LN_RX_S_CLKGATE_FRC_ON",
    "LN_RX_S_COMCLK_FRC_ON",
    "LN_RX_S_COMCLK_SEL",
    "LN_RX_S_PWRDN",
    "LN_RX_S_RSTB",
    "LN_S_RSTB",
    "LN_TX_DP_S_RSTB",
    "LN_TX_S_PWRDN",
    "LN_TX_S_RSTB",
    "LOST_PLL_LOCK_SM",
    "LOS_FILTER_COUNT",
    "LOS_THRESH",
    "MAX_PRBS_BURST_ERR_LENGTH_STATUS",
    "MDIO_ADDR_DATA",
    "MDIO_AER",
    "MDIO_BLK_ADDR",
    "MDIO_BRCST_PORT_ADDR",
    "MDIO_DEVAD",
    "MDIO_DEV_AN_EN",
    "MDIO_DEV_CL22_EN",
    "MDIO_DEV_DTE_EN",
    "MDIO_DEV_PCS_EN",
    "MDIO_DEV_PHY_EN",
    "MDIO_DEV_PMD_EN",
    "MDIO_FUNCTION",
    "MDIO_MASKDATA",
    "MDIO_MULTI_MMDS_EN",
    "MDIO_MULTI_PRTS_EN",
    "MEASURE_LFSR_CNT",
    "MEASURE_TIMEOUT",
    "MEAS_INCOMPLETE",
    "MICRO_AUTOINC_RDADDR_EN",
    "MICRO_AUTOINC_WRADDR_EN",
    "MICRO_CODE_RAM_ECC_ADDRESS",
    "MICRO_CODE_RAM_TM",
    "MICRO_CORE_CLK_EN",
    "MICRO_CORE_RSTB",
    "MICRO_DR_LOOKTAB_EN",
    "MICRO_DR_SIZE",
    "MICRO_ECCG_MODE",
    "MICRO_ECC_CORRUPT",
    "MICRO_ECC_FRC_DISABLE",
    "MICRO_GEN_INTR_RMI_MBOX0WR",
    "MICRO_GEN_INTR_RMI_MBOX1WR",
    "MICRO_M0_DEFAULT_SLAVE_ERROR",
    "MICRO_M0_HRESP_EN",
    "MICRO_MASTER_CLK_EN",
    "MICRO_MASTER_RSTB",
    "MICRO_PRAMIF_AHB_WRADDR_LSW",
    "MICRO_PRAMIF_AHB_WRADDR_MSW",
    "MICRO_PRAMIF_EN",
    "MICRO_PRAM_IF_RSTB",
    "MICRO_PR_AUTOINC_NXT_WRADDR_LSW",
    "MICRO_PR_DEFAULT_SLAVE_ERROR",
    "MICRO_PVT_TEMPDATA_FRC",
    "MICRO_PVT_TEMPDATA_FRCVAL",
    "MICRO_PVT_TEMPDATA_RMI",
    "MICRO_RA_AUTOINC_NXT_RDADDR_LSW",
    "MICRO_RA_AUTOINC_NXT_WRADDR_LSW",
    "MICRO_RA_ECC_RDDATA",
    "MICRO_RA_ECC_WRDATA",
    "MICRO_RA_INIT",
    "MICRO_RA_INITDONE",
    "MICRO_RA_RDADDR_LSW",
    "MICRO_RA_RDADDR_MSW",
    "MICRO_RA_RDDATASIZE",
    "MICRO_RA_RDDATA_LSW",
    "MICRO_RA_RDDATA_MSW",
    "MICRO_RA_WRADDR_LSW",
    "MICRO_RA_WRADDR_MSW",
    "MICRO_RA_WRDATASIZE",
    "MICRO_RA_WRDATA_LSW",
    "MICRO_RA_WRDATA_MSW",
    "MICRO_RMI_DEFAULT_SLAVE_ERROR",
    "MICRO_RMI_ECC_CORR_ERR_INTR_EN",
    "MICRO_RMI_ECC_CORR_ERR_STATUS",
    "MICRO_RMI_ECC_MULTIROW_ERR_INTR_EN",
    "MICRO_RMI_ECC_MULTIROW_ERR_STATUS",
    "MICRO_RMI_ECC_UNCORR_ERR_INTR_EN",
    "MICRO_RMI_ECC_UNCORR_ERR_STATUS",
    "MICRO_RMI_M0_LOCKUP_INTR_EN",
    "MICRO_RMI_M0_LOCKUP_STATUS",
    "MICRO_RMI_M0_SYSTEMRESETREQ_INTR_EN",
    "MICRO_RMI_M0_SYSTEMRESETREQ_STATUS",
    "MICRO_RMI_MBOX_MSGOUT_INTR_EN",
    "MICRO_RMI_MBOX_MSGOUT_STATUS",
    "MICRO_RMI_MBOX_SEND_MSGIN",
    "MICRO_RMI_TO_MICRO_MBOX0",
    "MICRO_RMI_TO_MICRO_MBOX1",
    "MICRO_SW_PMI_HP_EXT_RSTB",
    "MICRO_SW_PMI_HP_RSTB",
    "MICRO_TO_RMI_MBOX0",
    "MICRO_TO_RMI_MBOX1",
    "MICRO_TX_DISABLE",
    "OSR_MODE",
    "OSR_MODE_FRC",
    "OSR_MODE_FRC_VAL",
    "OSR_MODE_PIN",
    "OS_ALL_EDGES",
    "OS_PATTERN_ENHANCED",
    "PATT_GEN_EN",
    "PATT_GEN_SEQ_0",
    "PATT_GEN_SEQ_1",
    "PATT_GEN_SEQ_10",
    "PATT_GEN_SEQ_11",
    "PATT_GEN_SEQ_12",
    "PATT_GEN_SEQ_13",
    "PATT_GEN_SEQ_14",
    "PATT_GEN_SEQ_2",
    "PATT_GEN_SEQ_3",
    "PATT_GEN_SEQ_4",
    "PATT_GEN_SEQ_5",
    "PATT_GEN_SEQ_6",
    "PATT_GEN_SEQ_7",
    "PATT_GEN_SEQ_8",
    "PATT_GEN_SEQ_9",
    "PATT_GEN_START_POS",
    "PATT_GEN_STOP_POS",
    "PHASE_ERR_OFFSET",
    "PHASE_ERR_OFFSET_EN",
    "PHS_SUM_IGNORE_DSC_LOCK",
    "PLL_FORCE_CAP_DONE",
    "PLL_FORCE_CAP_DONE_EN",
    "PLL_FORCE_CAP_PASS",
    "PLL_FORCE_CAP_PASS_EN",
    "PLL_FORCE_FDONE",
    "PLL_FORCE_FDONE_EN",
    "PLL_FORCE_FPASS",
    "PLL_LOCK",
    "PLL_LOCK_FRC",
    "PLL_LOCK_FRC_VAL",
    "PLL_LOCK_LH_LL",
    "PLL_MODE",
    "PLL_SEQ_DONE",
    "PLL_SEQ_DONE_LH_LL",
    "PLL_SEQ_PASS",
    "PLL_SEQ_PASS_LH_LL",
    "PLL_SEQ_START",
    "PMD_CORE_DP_H_RSTB_PKILL",
    "PMD_CORE_MODE",
    "PMD_LANE_MODE",
    "PMD_LN_DP_H_RSTB_PKILL",
    "PMD_LN_H_RSTB_PKILL",
    "PMD_LN_RX_H_PWRDN_PKILL",
    "PMD_LN_TX_H_PWRDN_PKILL",
    "PMD_MDIO_TRANS_PKILL",
    "PMD_RX_CLK_VLD_FRC",
    "PMD_RX_CLK_VLD_FRC_VAL",
    "PMD_RX_LOCK",
    "PMD_RX_LOCK_CHANGE",
    "PMD_TX_CLK_VLD_FRC",
    "PMD_TX_CLK_VLD_FRC_VAL",
    "PMD_TX_DISABLE_PIN_DIS",
    "PRBS_BURST_ERR_LENGTH_STATUS",
    "PRBS_BURST_LEN_CHK_EN",
    "PRBS_CHK_CLK_EN_FRC_ON",
    "PRBS_CHK_EN",
    "PRBS_CHK_EN_AUTO_MODE",
    "PRBS_CHK_EN_TIMEOUT",
    "PRBS_CHK_EN_TIMER_MODE",
    "PRBS_CHK_ERR_CNT_BURST_MODE",
    "PRBS_CHK_ERR_CNT_LSB",
    "PRBS_CHK_ERR_CNT_MSB",
    "PRBS_CHK_INV",
    "PRBS_CHK_LOCK",
    "PRBS_CHK_LOCK_CNT",
    "PRBS_CHK_LOCK_LOST_LH",
    "PRBS_CHK_MODE",
    "PRBS_CHK_MODE_SEL",
    "PRBS_CHK_OOL_CNT",
    "PRBS_GEN_EN",
    "PRBS_GEN_ERR_INS",
    "PRBS_GEN_INV",
    "PRBS_GEN_MODE_SEL",
    "PRESET_DSC_AFE_BANK",
    "PRESET_DSC_A_BANK",
    "PRESET_DSC_C_BANK",
    "PRESET_DSC_D_BANK",
    "PRE_FREQ_DET_TIME",
    "PWRDN_SEQ_TIMER",
    "REFCLK_DIVCNT",
    "REFCLK_DIVCNT_SEL",
    "RESCAL_FRC",
    "RESCAL_FRC_VAL",
    "RESCAL_IN",
    "RESTART_PI_EXT_MODE",
    "RESTART_PMD_RESTART",
    "RESTART_SIGDET",
    "RES_CAL_CNTR",
    "RETRY_TIME",
    "REVID2",
    "REVID_BONDING",
    "REVID_CL72",
    "REVID_EEE",
    "REVID_LLP",
    "REVID_MDIO",
    "REVID_MICRO",
    "REVID_MODEL",
    "REVID_MULTIPLICITY",
    "REVID_PIR",
    "REVID_PROCESS",
    "REVID_REV_LETTER",
    "REVID_REV_NUMBER",
    "RMT_LPBK_EN",
    "RMT_LPBK_PD_EARLY_IND",
    "RMT_LPBK_PD_FRC_ON",
    "RMT_LPBK_PD_LATE_IND",
    "RMT_LPBK_PD_MODE",
    "RST_SEQ_DIS_FLT_MODE",
    "RST_SEQ_TIMER",
    "RXA_DFE_TAP10",
    "RXA_DFE_TAP10_MUX",
    "RXA_DFE_TAP11",
    "RXA_DFE_TAP11_MUX",
    "RXA_DFE_TAP12",
    "RXA_DFE_TAP12_MUX",
    "RXA_DFE_TAP13",
    "RXA_DFE_TAP13_MUX",
    "RXA_DFE_TAP14",
    "RXA_DFE_TAP14_MUX",
    "RXA_DFE_TAP2",
    "RXA_DFE_TAP3",
    "RXA_DFE_TAP4",
    "RXA_DFE_TAP5",
    "RXA_DFE_TAP6",
    "RXA_DFE_TAP7",
    "RXA_DFE_TAP7_MUX",
    "RXA_DFE_TAP8",
    "RXA_DFE_TAP8_MUX",
    "RXA_DFE_TAP9",
    "RXA_DFE_TAP9_MUX",
    "RXA_SLICER_OFFSET_ADJ_DN",
    "RXA_SLICER_OFFSET_ADJ_DP",
    "RXA_SLICER_OFFSET_ADJ_LMS",
    "RXA_SLICER_OFFSET_ADJ_ZN",
    "RXA_SLICER_OFFSET_ADJ_ZP",
    "RXB_DFE_TAP10",
    "RXB_DFE_TAP10_MUX",
    "RXB_DFE_TAP11",
    "RXB_DFE_TAP11_MUX",
    "RXB_DFE_TAP12",
    "RXB_DFE_TAP12_MUX",
    "RXB_DFE_TAP13",
    "RXB_DFE_TAP13_MUX",
    "RXB_DFE_TAP14",
    "RXB_DFE_TAP14_MUX",
    "RXB_DFE_TAP2",
    "RXB_DFE_TAP3",
    "RXB_DFE_TAP4",
    "RXB_DFE_TAP5",
    "RXB_DFE_TAP6",
    "RXB_DFE_TAP7",
    "RXB_DFE_TAP7_MUX",
    "RXB_DFE_TAP8",
    "RXB_DFE_TAP8_MUX",
    "RXB_DFE_TAP9",
    "RXB_DFE_TAP9_MUX",
    "RXB_SLICER_OFFSET_ADJ_DN",
    "RXB_SLICER_OFFSET_ADJ_DP",
    "RXB_SLICER_OFFSET_ADJ_LMS",
    "RXB_SLICER_OFFSET_ADJ_ZN",
    "RXB_SLICER_OFFSET_ADJ_ZP",
    "RXC_DFE_TAP10",
    "RXC_DFE_TAP10_MUX",
    "RXC_DFE_TAP11",
    "RXC_DFE_TAP11_MUX",
    "RXC_DFE_TAP12",
    "RXC_DFE_TAP12_MUX",
    "RXC_DFE_TAP13",
    "RXC_DFE_TAP13_MUX",
    "RXC_DFE_TAP14",
    "RXC_DFE_TAP14_MUX",
    "RXC_DFE_TAP2",
    "RXC_DFE_TAP3",
    "RXC_DFE_TAP4",
    "RXC_DFE_TAP5",
    "RXC_DFE_TAP6",
    "RXC_DFE_TAP7",
    "RXC_DFE_TAP7_MUX",
    "RXC_DFE_TAP8",
    "RXC_DFE_TAP8_MUX",
    "RXC_DFE_TAP9",
    "RXC_DFE_TAP9_MUX",
    "RXC_SLICER_OFFSET_ADJ_DN",
    "RXC_SLICER_OFFSET_ADJ_DP",
    "RXC_SLICER_OFFSET_ADJ_LMS",
    "RXC_SLICER_OFFSET_ADJ_ZN",
    "RXC_SLICER_OFFSET_ADJ_ZP",
    "RXD_DFE_TAP10",
    "RXD_DFE_TAP10_MUX",
    "RXD_DFE_TAP11",
    "RXD_DFE_TAP11_MUX",
    "RXD_DFE_TAP12",
    "RXD_DFE_TAP12_MUX",
    "RXD_DFE_TAP13",
    "RXD_DFE_TAP13_MUX",
    "RXD_DFE_TAP14",
    "RXD_DFE_TAP14_MUX",
    "RXD_DFE_TAP2",
    "RXD_DFE_TAP3",
    "RXD_DFE_TAP4",
    "RXD_DFE_TAP5",
    "RXD_DFE_TAP6",
    "RXD_DFE_TAP7",
    "RXD_DFE_TAP7_MUX",
    "RXD_DFE_TAP8",
    "RXD_DFE_TAP8_MUX",
    "RXD_DFE_TAP9",
    "RXD_DFE_TAP9_MUX",
    "RXD_SLICER_OFFSET_ADJ_DN",
    "RXD_SLICER_OFFSET_ADJ_DP",
    "RXD_SLICER_OFFSET_ADJ_LMS",
    "RXD_SLICER_OFFSET_ADJ_ZN",
    "RXD_SLICER_OFFSET_ADJ_ZP",
    "RX_DATA_15_TO_0",
    "RX_DATA_35_TO_20",
    "RX_DATA_THRESH_SEL",
    "RX_DSC_LOCK",
    "RX_DSC_LOCK_FRC",
    "RX_DSC_LOCK_FRC_VAL",
    "RX_LMS_THRESH_SEL",
    "RX_PF2_CTRL",
    "RX_PF_CTRL",
    "RX_PHASE_THRESH_SEL",
    "RX_PI_CNT_BIN_D",
    "RX_PI_CNT_BIN_DQ",
    "RX_PI_CNT_BIN_D_LD",
    "RX_PI_CNT_BIN_D_PD",
    "RX_PI_CNT_BIN_L",
    "RX_PI_CNT_BIN_LQ",
    "RX_PI_CNT_BIN_L_LD",
    "RX_PI_CNT_BIN_P",
    "RX_PI_CNT_BIN_PQ",
    "RX_PI_CNT_BIN_P_PD",
    "RX_PI_MANUAL_MODE",
    "RX_PI_MANUAL_STROBE",
    "RX_PI_PHASE_STEP_CNT",
    "RX_PI_PHASE_STEP_DIR",
    "RX_PI_SLICERS_EN",
    "RX_PMD_DP_INVERT",
    "RX_RESTART_PMD",
    "RX_RESTART_PMD_HOLD",
    "RX_VGA_CTRL",
    "RX_VGA_CTRL_VAL",
    "SDK_TX_DISABLE",
    "SET_MEAS_INCOMPLETE",
    "SIGDET_DP_RSTB_EN",
    "SIGNAL_DETECT",
    "SIGNAL_DETECT_CHANGE",
    "SIGNAL_DETECT_FILTER_1US",
    "SIGNAL_DETECT_FILTER_COUNT",
    "SIGNAL_DETECT_FRC",
    "SIGNAL_DETECT_FRC_VAL",
    "SIGNAL_DETECT_RAW",
    "SIGNAL_DETECT_RAW_CHANGE",
    "SIGNAL_DETECT_THRESH",
    "SLOWDN_XOR",
    "SUP_RST_SEQ_FRC",
    "SUP_RST_SEQ_FRC_VAL",
    "TDT_BIT_SEL",
    "TDT_CYCLE_BIN",
    "TDT_CYCLE_SEL",
    "TDT_PRBS_MODE",
    "TDT_PRBS_SLIP",
    "TDT_TRNSUM_EN",
    "THRESH_STEP_SIZE",
    "THRESH_TIMER_T1",
    "TIMER_DONE_FRC",
    "TIMER_DONE_FRC_VAL",
    "TLB_RX_DIFF_DEC_EN",
    "TLB_TX_DIFF_ENC_EN",
    "TRNSUM",
    "TRNSUM_A",
    "TRNSUM_A_LOW",
    "TRNSUM_B",
    "TRNSUM_B_LOW",
    "TRNSUM_C",
    "TRNSUM_CLR_FRC",
    "TRNSUM_CLR_FRC_VAL",
    "TRNSUM_COR_SEL",
    "TRNSUM_C_LOW",
    "TRNSUM_D",
    "TRNSUM_D_LOW",
    "TRNSUM_EDGE_PATTERN_EN",
    "TRNSUM_EN",
    "TRNSUM_ERROR_COUNT_EN",
    "TRNSUM_EYE_CLOSURE_EN",
    "TRNSUM_FRZ_FRC",
    "TRNSUM_FRZ_FRC_VAL",
    "TRNSUM_GAIN",
    "TRNSUM_INV_PATTERN_EN",
    "TRNSUM_LOW",
    "TRNSUM_PATTERN",
    "TRNSUM_PATTERN_BIT_EN",
    "TRNSUM_PATTERN_FULL_CHECK_OFF",
    "TRNSUM_QPHASE_MULT_EN",
    "TRNSUM_RANDOM_TAPSEL_DISABLE",
    "TRNSUM_SEL_EMUX",
    "TRNSUM_TAP_EN",
    "TRNSUM_TAP_RANGE_SEL",
    "TRNSUM_TAP_SIGN",
    "TXCOM_CL93N72_MAX_WAIT_TIMER_PERIOD",
    "TXCOM_CL93N72_WAIT_CNTR_LIMIT",
    "TXCOM_MAIN_TAP_ALERT_VAL",
    "TXCOM_POST_TAP_ALERT_VAL",
    "TXCOM_PRE_TAP_ALERT_VAL",
    "TXFIR_MAIN_ADJUSTED",
    "TXFIR_MAIN_AFTER_OVR",
    "TXFIR_MAIN_OFFSET",
    "TXFIR_POST2",
    "TXFIR_POST2_ADJUSTED",
    "TXFIR_POST2_OFFSET",
    "TXFIR_POST3",
    "TXFIR_POST3_ADJUSTED",
    "TXFIR_POST3_OFFSET",
    "TXFIR_POST_ADJUSTED",
    "TXFIR_POST_AFTER_OVR",
    "TXFIR_POST_OFFSET",
    "TXFIR_PRE_ADJUSTED",
    "TXFIR_PRE_AFTER_OVR",
    "TXFIR_PRE_OFFSET",
    "TX_DISABLE_OUTPUT_SEL",
    "TX_DISABLE_TIMER_CTRL",
    "TX_EEE_ALERT_EN",
    "TX_EEE_QUIET_EN",
    "TX_LANE_MAP_0",
    "TX_LANE_MAP_1",
    "TX_LANE_MAP_2",
    "TX_LANE_MAP_3",
    "TX_MUX_SEL_ORDER",
    "TX_PCS_NATIVE_ANA_FRMT_EN",
    "TX_PI_EN",
    "TX_PI_EXT_CTRL_EN",
    "TX_PI_EXT_PHASE_BWSEL_INTEG",
    "TX_PI_FIRST_ORDER_BWSEL_INTEG",
    "TX_PI_FREQ_OVERRIDE_EN",
    "TX_PI_FREQ_OVERRIDE_VAL",
    "TX_PI_FRZ_FRC",
    "TX_PI_FRZ_FRC_VAL",
    "TX_PI_FRZ_MODE",
    "TX_PI_INTEG1_REG",
    "TX_PI_INTEG2_REG",
    "TX_PI_JITTER_FILTER_EN",
    "TX_PI_JIT_AMP",
    "TX_PI_JIT_FREQ_IDX",
    "TX_PI_JIT_SSC_FREQ_MODE",
    "TX_PI_LOOP_FILTER_STABLE",
    "TX_PI_LOOP_TIMING_SRC_SEL",
    "TX_PI_PHASE_CNTR",
    "TX_PI_PHASE_ERR",
    "TX_PI_PHASE_INVERT",
    "TX_PI_PHASE_OVERRIDE",
    "TX_PI_PHASE_STEP_DIR",
    "TX_PI_PHASE_STEP_NUM",
    "TX_PI_PHASE_STROBE",
    "TX_PI_RESET_CODE_DBG",
    "TX_PI_RMT_LPBK_BYPASS_FLT",
    "TX_PI_SECOND_ORDER_BWSEL_INTEG",
    "TX_PI_SECOND_ORDER_LOOP_EN",
    "TX_PI_SJ_GEN_EN",
    "TX_PI_SSC_GEN_EN",
    "TX_PMD_DP_INVERT",
    "TX_S_CLKGATE_FRC_ON",
    "TX_S_COMCLK_FRC_ON",
    "TX_S_COMCLK_SEL",
    "UC_ACK_CORE_CFG_DONE",
    "UC_ACK_CORE_DP_RESET",
    "UC_ACK_DSC_CONFIG",
    "UC_ACK_DSC_EEE_DONE",
    "UC_ACK_DSC_RESTART",
    "UC_ACK_LANE_CFG_DONE",
    "UC_ACK_LANE_DP_RESET",
    "UC_ACTIVE",
    "UC_DSC_ERROR_FOUND",
    "UC_DSC_GP_UC_REQ",
    "UC_DSC_READY_FOR_CMD",
    "UC_DSC_SCRATCH",
    "UC_DSC_SUPP_INFO",
    "UC_TRNSUM_EN",
    "UC_TUNE_EN",
    "VCO_DONE_EN",
    "VCO_RANGE_ADJUST",
    "VCO_RST_EN",
    "VCO_START_TIME",
    "VCO_STEP_TIME",
    "VGA_DEC",
    "VGA_INC",
    "VGA_TIMER_T2",
    "VGA_WRITE",
    "WIN_CAL_CNTR",
};

#endif
#endif
#endif
#endif /* PHYMOD_CONFIG_INCLUDE_FIELD_INFO */



/*******************************************************************************
 *
 * The following is the symbol table itself. 
 * It defines the entries for all registers and memories.
 * It also incorporates the field information for each register and memory if
 * applicable.
 */
static const phymod_symbol_t bcmi_falcon_xgxs_syms[] = {
#ifndef PHYMOD_CONFIG_EXCLUDE_CHIP_SYMBOLS_BCMI_FALCON_XGXS
{
	BCMI_FALCON_XGXS_ACC_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_ACC_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ACC_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_CL22_IEEE_COM_ACC_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_ACC_ADDR_DATAr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_ACC_ADDR_DATAr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"ACC_ADDR_DATAr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_CL22_IEEE_COM_ACC_ADDR_DATA",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_PMD_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_CONTROL_REGISTER_150",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_PMD_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_PMD_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_PMD_STATUS_REGISTER_151",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_COEFF_UPDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IR_BASE_R_LP_COEFF_UPDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IR_BASE_R_LP_STS_REPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IR_BASE_R_LP_STS_REPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_RX_CL93N72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_COEFF_UPDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_LD_COEFF_UPDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_IT_BASE_R_LD_STS_REPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_IT_BASE_R_LD_STS_REPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_IEEE_TX_CL93N72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PF_CTL_DC_OFFSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PF_CTL_DC_OFFSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RX_PF_CTRL_DC_OFFSET",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_DN_DPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXA_SLCR_OFFS_ADJ_DN_DPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXA_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXA_SLCR_OFFS_ADJ_ZN_ZPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXA_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXAB_SLCR_OFFS_ADJ_LMSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXAB_SLCR_OFFS_ADJ_LMSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXAB_SLICER_OFFSET_ADJ_LMS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_DN_DPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXB_SLCR_OFFS_ADJ_DN_DPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXB_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXB_SLCR_OFFS_ADJ_ZN_ZPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXB_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_DN_DPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXC_SLCR_OFFS_ADJ_DN_DPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXC_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXC_SLCR_OFFS_ADJ_ZN_ZPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXC_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXCD_SLCR_OFFS_ADJ_LMSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXCD_SLCR_OFFS_ADJ_LMSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXCD_SLICER_OFFSET_ADJ_LMS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_DN_DPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXD_SLCR_OFFS_ADJ_DN_DPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXD_SLICER_OFFSET_ADJ_DN_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RXD_SLCR_OFFS_ADJ_ZN_ZPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RXD_SLICER_OFFSET_ADJ_ZN_ZP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PHASE_LMS_THR_SELr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PHASE_LMS_THR_SELr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE1_RX_PHASE_LMS_THRESH_SEL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_ABr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP2_ABr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP2_AB",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP2_CDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP2_CDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP2_CD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_ABr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP3_ABr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP3_AB",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP3_CDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP3_CDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP3_CD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP4_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP4_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP4_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP5_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP5_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP5_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP6_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP6_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP6_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP7_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP7_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP8_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP8_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP8_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP9_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE2_RX_DFE_TAP9_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP10_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP10_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP10_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP11_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP11_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP12_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP12_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP12_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP13_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP13_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP14_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP14_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP14_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP7_8_MUX_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP7_8_MUX_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP7_8_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP9_10_MUX_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP9_10_MUX_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP9_10_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP11_12_MUX_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP11_12_MUX_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP11_12_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DFE_TAP13_14_MUX_ABCDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DFE_TAP13_14_MUX_ABCDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_RX_DFE_TAP13_14_MUX_ABCD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_LOAD_PRESETSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_LOAD_PRESETSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_AFE3_LOAD_PRESETS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_UC_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_UC_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_UC_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_A_DSC_UC_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SCRATCHr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SCRATCHr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SCRATCHr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_A_DSC_SCRATCH",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_A_LOr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_A_LOr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_A_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_Ar,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_Ar_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_Ar",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_A",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_B_LOr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_B_LOr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_B_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_Br,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_Br_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_Br",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_B",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_C_LOr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_C_LOr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_C_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_Cr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_Cr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_Cr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_C",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_D_LOr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_D_LOr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_D_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_Dr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_Dr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_Dr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_D",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_LOr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_LOr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_LOr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM_LOW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUMr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUMr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUMr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_TRNSUM",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_DC_OFFS_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DC_OFFS_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_DC_OFFSET_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_VGA_D_THR_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_VGA_D_THR_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_B_VGA_D_THRESH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2700, /* 9984 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x9, /* 9 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_CDR_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x80, /* 128 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_RX_PI_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_PAT_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_PAT_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_PAT_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_PAT_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_PAT_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_TAP_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_TAP_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_TAP_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_TDT_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_TDT_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_TDT_CTL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_TRNSUM_MISCr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_TRNSUM_MISCr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_TRNSUM_MISC",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_VGA_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_VGA_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_VGA_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_VGA_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_DATA_SLCR_THR_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DATA_SLCR_THR_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_DATA_SLICER_THRESH_CTRL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_DC_OFFS_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_DC_OFFS_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_C_DC_OFFSET_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8, /* 8 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x200, /* 512 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x87, /* 135 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1c1e, /* 7198 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL5r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL5r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL5r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x35ad, /* 13741 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL6r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL6r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL6r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x340d, /* 13325 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL7r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL7r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL7r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL8r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL8r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL8r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x11, /* 17 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_CTL9r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_CTL9r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_CTL9r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_CTRL_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_LOCKr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_LOCKr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_LOCK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_ONE_HOTr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_ST_ONE_HOTr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE_ONE_HOT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_ST_EEE_ONE_HOTr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_ST_EEE_ONE_HOTr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_STS_RESTARTr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_RESTARTr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_RESTART",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_SM_STS_DSC_STr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_SM_STS_DSC_STr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_D_DSC_SM_STATUS_DSC_STATE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_PDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_PDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_PD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_LDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_LDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_LD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DATA_15_TO0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DATA_15_TO0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_DATA_15_TO_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_DATA_35_TO_20r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_DATA_35_TO_20r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_DATA_35_TO_20",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_STS_PHASE_ERRr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_PHASE_ERRr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_PHASE_ERROR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Dr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_Dr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_D",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Pr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_Pr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_P",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_RX_PI_CNT_BIN_Lr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_RX_PI_CNT_BIN_Lr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_RX_PI_CNT_BIN_L",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_STS_INTEGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_INTEGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_INTEG_REG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_STS_MISCr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_STS_MISCr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_STATUS_MISC",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_CDR_1G_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_CDR_1G_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_CDR_1G_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_CDR_1G_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DSC_PRESETr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DSC_PRESETr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DSC_PRESETr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DSC_E_PRESET_REG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x52, /* 82 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x310, /* 784 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_UC_INTR_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_INTR_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_INTERRUPT_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_UC_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UR_UC_STS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UR_UC_STS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_RX_CL93N72UR_MICRO_STATUS1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_XMT_UPD_PAGEr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_XMT_UPD_PAGEr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_XMT_UPDATE_PAGE_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_LD_XMT_STS_PAGEr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_LD_XMT_STS_PAGEr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_LD_XMT_STATUS_PAGE",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2c08, /* 11272 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_CONTROL3_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3c, /* 60 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CL93N72_UT_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CL93N72_UT_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CL93N72_UT_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CL93N72_USER_TX_CL93N72UT_STATUS0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7000, /* 28672 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x100, /* 256 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_CTL4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_CTL4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4, /* 4 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_STS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_STS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_STS2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_STS2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_PI_PMD_STS3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_PI_PMD_STS3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_PI_PMD_STS3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_PI_PMD_COM_STATUS_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_CLK_RST_N_PWRDWN_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_CLK_RST_N_PWRDWN_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_CLK_RESET_N_POWERDOWN_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_AFE_RST_PWRDWN_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_AFE_RST_PWRDWN_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_AFE_RESET_PWRDWN_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_RST_N_PWRDN_PIN_KILL_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_DBG_RST_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_DBG_RST_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_DEBUG_RESET_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x303, /* 771 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_UC_ACK_LN_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_UC_ACK_LN_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_UC_ACK_LANE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_RST_OCC_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_RST_OCC_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_REG_RESET_OCCURRED_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_CLK_N_RST_DBG_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_CLK_N_RST_DBG_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_CLOCK_N_RESET_DEBUG_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_PMD_LN_MODE_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_PMD_LN_MODE_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_PMD_LANE_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_DP_RST_ST_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_DP_RST_ST_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LANE_DP_RESET_STATE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_MASKr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_MASKr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_MASKr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LN_MASK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_OSR_MODE_PIN_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_OSR_MODE_PIN_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_OSR_MODE_PIN_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_CKRST_LN_S_RSTB_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"CKRST_LN_S_RSTB_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"CKRST_CTRL_PMD_LN_S_RSTB_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x10, /* 16 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xe00, /* 3584 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL5r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL5r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL5r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL6r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL6r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL6r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL7r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL7r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL7r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL8r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL8r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL8r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_CTL9r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_CTL9r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_CTL9r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_CONTROL_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x300, /* 768 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_RX_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_RX_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_RX_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_RX_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_TX_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_TX_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc0, /* 192 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_TX_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_TX_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2000, /* 8192 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_TX_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_TX_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xf, /* 15 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_TX_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_TX_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_TX_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_TX_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_TX_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_TX_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa0, /* 160 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_SIGDET_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_SIGDET_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1109, /* 4361 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_SIGDET_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_SIGDET_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa008, /* 40968 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_SIGDET_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_SIGDET_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_CTRL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3f22, /* 16162 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_SIGDET_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_SIGDET_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"SIGDET_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"SIGDET_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x200, /* 512 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_REVID0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_REVID0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2db, /* 731 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_RST_CTL_PMDr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_CTL_PMDr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RESET_CONTROL_PMD",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_RST_CTL_CORE_DPr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_CTL_CORE_DPr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RESET_CONTROL_CORE_DP",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x4000, /* 16384 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_LN_MASKr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_LN_MASKr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_LN_MASKr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_LANE_MASK",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_TOP_USER_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TOP_USER_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TOP_USER_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x271, /* 625 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_UC_ACK_CORE_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_UC_ACK_CORE_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_UC_ACK_CORE_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_CORE_RST_OCC_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_CORE_RST_OCC_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_RST_SEQ_TMR_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_RST_SEQ_TMR_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_RST_SEQ_TIMER_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8304, /* 33540 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_CORE_DP_RST_ST_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_CORE_DP_RST_ST_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_CORE_DP_RESET_STATE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_PMD_CORE_MODE_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_PMD_CORE_MODE_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_PMD_CORE_MODE_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_REVID1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_REVID1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x403c, /* 16444 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_TX_LN_MAP_0_1_2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TX_LN_MAP_0_1_2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TX_LANE_MAP_0_1_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x820, /* 2080 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_TX_LN_MAP_3_N_LN_ADDR_0_1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_TX_LANE_MAP_3_N_LANE_ADDR_0_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x403, /* 1027 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_LN_ADDR_2_3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_LN_ADDR_2_3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_LANE_ADDR_2_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x302, /* 770 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_DIG_REVID2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_DIG_REVID2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"DIG_REVID2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"DIG_COM_REVID2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1e, /* 30 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x77, /* 119 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL5r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL5r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL5r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f00, /* 7936 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL6r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL6r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL6r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc1c0, /* 49600 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_CTL7r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_CTL7r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_CTL7r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_CONTROL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f00, /* 7936 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_AMS_PLL_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_AMS_PLL_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"AMS_PLL_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"AMS_COM_PLL_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc007, /* 49159 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ5r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ5r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ5r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ6r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ6r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ6r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ7r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ7r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ7r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ8r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ8r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ8r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_8",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ9r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ9r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ9r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_9",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_10r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_10r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_10",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_11r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_11r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_11",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_12r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_12r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_12",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_13r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_13r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_13",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PATT_GEN_SEQ_14r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PATT_GEN_SEQ_14r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PATT_GEN_COM_SEQ_14",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff00, /* 65280 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_CONTROL2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x800, /* 2048 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2c08, /* 11272 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_STS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_STS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3c, /* 60 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_STS2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_STS2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2c08, /* 11272 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_STS3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_STS3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x3c, /* 60 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_STS4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_STS4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_STS4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_STATUS4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8, /* 8 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_UC_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_UC_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_UC_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_MICRO_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TXFIR_MISC_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TXFIR_MISC_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_FED_TXFIR_MISC_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x300, /* 768 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc803, /* 51203 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc8ff, /* 51455 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_2",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xff01, /* 65281 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_3",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL4r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL4r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL4r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_4",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa80d, /* 43021 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL5r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL5r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL5r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_5",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x27, /* 39 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL6r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL6r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL6r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_6",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL7r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL7r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL7r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_7",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_PLL_CAL_CTL_STS_DBGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"PLL_CAL_CTL_STS_DBGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"PLL_CAL_COM_CTL_STATUS_DBG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1, /* 1 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL0_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL1_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x70, /* 112 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_CTL2r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_CTL2r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL2r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL2_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f4, /* 500 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TX_CTL3r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TX_CTL3r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TX_CTL3r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TX_COM_CONTROL3_REGISTER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xc8, /* 200 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CNT_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_CNT_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_CNT_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x602, /* 1538 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x10a, /* 266 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_DIG_LPBK_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_DIG_LPBK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa, /* 10 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_MISC_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_MISC_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_MISC_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_EN_TMR_CTLr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_EN_TMR_CTLr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_EN_TIMER_CONTROL",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_DIG_LPBK_PD_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_DIG_LPBK_PD_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_DIG_LPBK_PD_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_LOCK_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_LOCK_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_LOCK_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_ERR_CNT_MSB_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x8000, /* 32768 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_CHK_ERR_CNT_LSB_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PMD_RX_LOCK_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PMD_RX_LOCK_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PMD_RX_LOCK_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_PRBS_BURST_ERR_LEN_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_PRBS_BURST_ERR_LEN_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_PRBS_BURST_ERR_LENGTH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_RX_MAX_PRBS_BURST_ERR_LEN_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_RX_MAX_PRBS_BURST_ERR_LENGTH_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_TX_PATT_GEN_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_PATT_GEN_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_PATT_GEN_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xb000, /* 45056 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_TX_PRBS_GEN_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_PRBS_GEN_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_PRBS_GEN_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0xa, /* 10 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_RMT_LPBK_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_RMT_LPBK_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_TX_MISC_CFGr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_MISC_CFGr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_MISC_CONFIG",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_TLB_TX_RMT_LPBK_PD_STSr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"TLB_TX_RMT_LPBK_PD_STSr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"TLB_TX_RMT_LPBK_PD_STATUS",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x2, /* 2 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CLK_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CLK_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CLK_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_CLOCK_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RST_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RST_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RST_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_RESET_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_WRADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_WRADDR_MSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRADDR_MSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_WRDATA_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRDATA_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRDATA_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_WRDATA_MSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_WRDATA_MSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_WRDATA_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_RDADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_RDADDR_MSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDADDR_MSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_RDDATA_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDDATA_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDDATA_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_AHB_RDDATA_MSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_AHB_RDDATA_MSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_AHB_RDDATA_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_PRAMIF_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_AHB_WRADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_PRAMIF_AHB_WRADDR_MSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PRAMIF_AHB_WRADDR_MSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_PVT_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_PVT_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_PVT_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_PVT_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_TO_UC_MBOX0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_TO_MICRO_MBOX0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_TO_UC_MBOX1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_TO_UC_MBOX1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_TO_MICRO_MBOX1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_UC_TO_RMI_MBOX0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_MICRO_TO_RMI_MBOX0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_UC_TO_RMI_MBOX1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_UC_TO_RMI_MBOX1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_MICRO_TO_RMI_MBOX1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_MBOX_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_MBOX_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_MBOX_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_AHB_CTL1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_AHB_CTL1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_AHB_CONTROL1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x7, /* 7 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_AHB_STS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_AHB_STS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_AHB_STATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_WRADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_RA_AINC_NXT_WRADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_RA_AINC_NXT_RDADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_RA_AINC_NXT_RDADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_PR_AINC_NXT_WRADDR_LSWr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_PR_AINC_NXT_WRADDR_LSWr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_PVT_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_PVT_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_B_COM_RMI_PVT_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCCTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCCONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCCONTRO1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCCONTRO1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCCONTRO1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCSTS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCSTATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CODE_RAM_ECCSTS1r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_ECCSTS1r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_ECCSTATUS1",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_CODE_RAM_TESTIFCTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_CODE_RAM_TESTIFCTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_CODE_RAM_TESTIFCONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RAM_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RAM_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RAM_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RAM_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x401, /* 1025 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_CTL0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_EXT_INTR_CTL0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RMI_EXT_INTR_CONTROL0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_UC_RMI_EXT_INTR_STS0r_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"UC_RMI_EXT_INTR_STS0r",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MICRO_C_COM_RMI_EXT_INTR_STATUS0",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_MDIO_MASKDATAr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_MDIO_MASKDATAr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_MASKDATAr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_MASKDATA",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_MDIO_BCST_PORT_ADDRr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_BCST_PORT_ADDRr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x1f, /* 31 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_MDIO_MMD_SELr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_MDIO_MMD_SELr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_MMD_SELr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_MMD_SELECT",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x404d, /* 16461 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_MDIO_AERr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_MDIO_AERr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_AERr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_MMDSEL_AER_COM_MDIO_AER",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
{
	BCMI_FALCON_XGXS_MDIO_BLK_ADDRr,
#if  PHYMOD_CONFIG_INCLUDE_FIELD_INFO == 1
#ifndef PHYMOD_CONFIG_EXCLUDE_FIELD_INFO_BCMI_FALCON_XGXS
	BCMI_FALCON_XGXS_MDIO_BLK_ADDRr_fields,
#else
	0,
#endif
#endif
	 PHYMOD_SYMBOL_INDEX_SIZE_ENCODE(1),
	PHYMOD_SYMBOL_FLAG_REGISTER,
	"MDIO_BLK_ADDRr",
#if  PHYMOD_CONFIG_INCLUDE_ALIAS_NAMES == 1
	"MDIO_BLK_ADDR_COM_BLK_ADDR",
	NULL,
#endif
#if  PHYMOD_CONFIG_INCLUDE_RESET_VALUES == 1
	0x0, /* 0 */
	0,
#endif
},
#endif
};


phymod_symbols_t bcmi_falcon_xgxs_symbols = 
{
   bcmi_falcon_xgxs_syms, sizeof(bcmi_falcon_xgxs_syms)/sizeof(bcmi_falcon_xgxs_syms[0]),
#if PHYMOD_CONFIG_INCLUDE_FIELD_NAMES == 1
   bcmi_falcon_xgxs_fields
#else
   NULL
#endif
/* END OF SYMBOL FILE */
};

#endif /* PHYMOD_CONFIG_INCLUDE_CHIP_SYMBOLS */
